1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D
D
C
C
B
B
A
A
3
of
4
P
IC16
F
152
76
Cu
rio
si
ty
Na
n
o
15
.1
2.
20
20
P
IC1
6F
15
27
6_
Cu
ri
os
ity
_N
an
o_
D
eb
ug
ge
r.S
ch
D
oc
Pr
oj
ec
t T
itl
e
PC
B
A
ss
em
bly
N
umber:
PC
B
A
Re
vis
ion:
File
:
PC
B
Nu
mber:
PCB
Revision:
Design
ed w
ith
Drawn
By:
ST
Sh
ee
t T
itle
Deb
ug
ger
E
ng
ineer:
T
F
A
08-3132
1
Size
A
3
A
09-3431
1
Pa
ge:
Date
:
A
lti
um
.c
om
DE
BUG
G
E
R
U
SB
M
IC
R
O
-B C
O
N
NE
C
T
O
R
GND
U
SBD_P
U
SBD_N
100n
C107
100n
C108
1k
R107
VCC_P3V3
SR
ST
ST
A
T
U
S_
L
ED
SH
IE
L
D
V
B
U
S
VCC_P3V3
GND
TP100
Te
st
po
in
t A
rray
1
2
3
4
5
6
7
8
9
1
0
TCK
TDO
T
M
S
Vsup
T
D
I
GND
T
R
ST
SR
ST
V
T
ref
GND
J102
GND
4.
7u
F
C100
D
B
G
0
DBG0
2
1
GR
EEN
LED
SM
L
-P12MTT86R
D100
V
B
U
S
1
D
-
2
D
+
3
G
N
D
5
S
H
I
E
L
D1
6
S
H
I
E
L
D2
7
I
D
4
S
H
I
E
L
D3
8
S
H
I
E
L
D4
9
MU
-M
B0
14
2A
B2-269
J105
P
A
D
3
3
P
A
0
0
1
P
A
0
1
2
P
A
0
2
3
P
A
0
3
4
GN
D
10
VD
DA
NA
9
P
A
0
4
5
P
A
0
5
6
P
A
0
6
7
P
A
0
7
8
PA
08
11
PA
09
12
PA
10
13
PA
11
14
PA
14
15
PA
15
16
P
A
1
6
1
7
P
A
1
7
1
8
P
A
1
8
1
9
P
A
1
9
2
0
P
A
2
2
2
1
U
S
B
_
S
OF
/
P
A
2
3
2
2
U
S
B
_
D
M/
P
A
2
4
2
3
U
S
B
_
D
P/
P
A
2
5
2
4
PA
27
25
RE
SE
TN
26
PA
28
27
GN
D
28
VD
DC
ORE
29
VD
DI
N
30
SW
DC
LK
/P
A3
0
31
SW
DI
O/P
A3
1
32
SA
MD
21
E1
8A
-MUT
U100
V
O
U
T
1
V
O
U
T
2
GN
D
3
E
N
4
V
I
N
6
N
C
5
EP
7
M
IC5528-3.
3YMT
U101
VCC_P3V3
GND
U
SBD_P
U
SBD_N
GND
1u
C106
VCC_MC
U_COR
E
VCC_P3V3
VCC_P3V3
2.
2u
F
C101
GND
74
L
VC1T45FW
4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U103
VCC_P3V3
GND
74
L
VC1T45FW
4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U104
VCC_P3V3
GND
74
L
VC1T45FW
4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U105
VCC_P3V3
GND
GND
GND
GND
VCC_E
DGE
GND
74
L
VC1T45FW
4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U107
VCC_P3V3
GND
D
B
G
2
DB
G
3_
CT
RL
S1_0_TX
S1_1_RX
S0_2_TX
D
A
C
V
T
G
_A
DC
R
E
SE
R
VED
S0
_3
_C
L
K
DBG0_CTRL
CD
C_
TX
_C
TR
L
BOOT
D
E
B
U
G
G
E
R
P
O
W
E
R
/S
T
A
T
U
S
L
E
D
E
N
1
B
Y
P
6
V
O
U
T
4
G
N
D
2
V
I
N
3
N
C
/
A
D
J
5
G
N
D
7
M
IC5353
U102
100n
C102
GND
GND
47k
R101
27k
R104
GND
33
k
R106
2.
2u
F
C103
GND
1k
R108
J100
V
C
C
_L
E
V
E
L
VC
C_
RE
GU
LA
T
OR
74
L
VC1T45FW
4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U106
VCC_P3V3
GND
D
B
G
1
CDC_R
X
CDC_T
X
D
B
G
3
DBG1_CTRL
DE
BUG
G
E
R
R
E
G
U
L
A
T
O
R
REG_ENABL
E
R
EG
_E
N
AB
L
E
47k
R103
V
C
C
_L
E
V
E
L
V
C
C
_L
E
V
E
L
V
C
C
_L
E
V
E
L
V
C
C
_L
E
V
E
L
V
C
C
_L
E
V
E
L
47k
R102
47k
R105
SW
C
L
K
GND
47k
R100
GND
DBG2
S0_0_RX
DB
G
1_
CT
RL
DB
G
0_
CT
RL
DBG
3
O
P
E
N
DR
AI
N
T
A
R
G
E
T
A
D
JU
ST
A
B
L
E
R
E
G
U
L
A
T
O
R
SRS
T
DE
BUG
G
E
R
T
E
ST
P
O
INT
DBG2_CTRL
VOFF
CD
C_
RX
_C
TR
L
47k
R109
DBG1
CD
C_
TX
_C
TR
L
CD
C_
RX
_C
TR
L
SW
C
L
K
REG_ADJUST
DBG2_GPIO
DB
G
3_
CT
RL
DB
G
2_
CT
RL
DBG3
1k
R
110
VBUS_ADC
1
2
3
DM
N6
5D
8L
FB
Q101
I
D
_
S
Y
S
V
O
F
F
1k
R112
VCC_P3V3
V
T
G
_A
DC
D
A
C
M
IC94163
V
I
N
B
2
V
O
U
T
A
1
V
I
N
A
2
E
N
C
2
G
N
D
C
1
V
O
U
T
B
1
U108
GND
ID
_S
Y
S
VTG_EN
VTG_EN
VBUS_ADC
SW
D
IO
ID
_S
Y
S
TP101
GND
SW
D
IO
VOFF
47k
R111
GND
ID P
IN
V
CC
_VB
US
MC36213
F100
V
CC
_VB
US
V
CC
_VB
US
J101
V
C
C
_T
A
RGET
47
k
R
113
DEBUGGE
R
UP
DI
U
PD
I
G
PI
O
G
PI
O
R
E
SET
Signa
l
D
B
G
0
D
B
G
1
D
B
G
2
D
B
G
3
IC
SP
Inter
fa
ce
D
A
T
C
L
K
G
PI
O
M
C
L
R
C
DC
T
X
C
DC
R
X
U
A
R
T
RX
U
A
R
T
TX
U
A
R
T
RX
U
A
R
T
TX
T
A
R
G
E
T
T
A
R
G
E
T
VC
C
-
-
SW
D
SW
D
A
T
SW
C
L
K
SW
O
/G
PI
O
R
E
SET
U
A
R
T
RX
U
A
R
T
TX
T
A
R
G
E
T
-
C
D
C
_
T
X
C
D
C
_
R
X
A
VR® progr
amming
connector for factory
programming of
DEBUG
GER.
M
IC5528:
V
in: 2.5V t
o
5.
5V
V
ou
t: F
ix
ed
3
.3
V
Im
ax:
50
0mA
Drop
out:
260m
V
@ 500mA
M
IC5353:
V
in: 2.6V t
o
6V
V
out: 1.25V t
o
5.
1V
Im
ax:
50
0mA
Dropout (typi
cal):
50mV@
15
0mA
, 160mV
@ 500mA
A
ccurac
y:
2%
initi
al
T
he
rm
al shutd
own and c
urrent l
imit
M
ax
im
um
output vo
lta
ge is li
mited by
the in
put vol
ta
ge and
the dr
opo
ut vol
ta
ge in t
he
regu
la
to
r.
(V
m
ax
=
V
in -
d
ro
po
ut)
J100:
Cut-st
rap us
ed for
fu
ll se
paration
of
targ
et powe
r from the level
shifter
s and o
n-bo
ard regu
lator
s.
- Fo
r curren
t mea
su
re
men
ts
usi
ng
an
e
xte
rna
l p
ow
er
su
ppl
y,
th
is s
trap
c
ou
ld
b
e
cut
fo
r
mo
re
acc
ur
ate m
ea
su
re
ments. L
ea
ka
ge
bac
k t
hr
ou
gh t
he s
witc
h
is i
n
the
mic
ro
amp
ere r
ang
e.
J101:
This
is fo
otpri
nt
fo
r a 1
x2
10
0mil
pitc
h
pin-
heade
r
th
at c
an b
e use
d
for
easy
c
ur
rent
m
ea
su
re
me
nt
to the
targ
et
microc
ontroller and
the L
ED
/
B
ut
to
n.
T
o
use
the
f
oot
pr
int:
- Cut th
e track
betw
een
th
e
ho
les,
and
mo
unt a
pi
n-h
eade
r
A
djusta
ble output and limita
tions:
- The D
EBUGGER can
adjust
the ou
tput vol
ta
ge of t
he reg
ulator be
twee
n 1.25
V and 5
.1V
to th
e targ
et.
- T
he
vo
lta
ge output
is limited b
y the
input (
USB),
whic
h c
an v
ary betwe
en 4.40V
to
5
.2
5V
-
Th
e
le
vel shi
fters ha
ve a mi
ni
m
al
v
ol
ta
ge
le
vel of 1.
65V
and wil
l limit t
he mi
ni
m
um
op
erat
ing
vo
lta
ge
a
ll
ow
ed
f
or
th
e
ta
rg
et to
still all
ow comm
unicat
ion.
-
Th
e
MI
C94163 ha
s a mi
ni
m
al
vo
lat
eg
e
le
vel of 1.
70V
and wil
l limit t
he mi
ni
m
um
v
ol
ta
ge d
eli
vered to t
he targ
et
.
-
Fi
rm
ware
con
figurati
on will
limi
t the vo
lta
ge
ran
ge to
be w
ithi
n
th
e
the
targ
et spe
cific
ation
.
PTC Resett
able fu
se:
Hold curre
nt: 500mA
T
rip current
: 1000mA
R
113:
Pull down t
o preve
nt
D
B
G
3_
C
T
R
L
f
ro
m
fl
oat
in
g when debugg
er
is
no
t po
were
d.
Appendix
©
2021 Microchip Technology Inc.
User Guide
DS50003143A-page 29
