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HV2903 Analog Switch Evaluation Board User’s Guide
DS50002582A-page 17

2017 Microchip Technology Inc.
2.3.1 Recommended Power-Up and Power-Down Sequences
Table 2-2 shows the recommended power-up and power-down sequences of the
HV2903 Analog Switch Evaluation Board.
2.4 INTERFACE CONNECTIONS
TABLE 2-2: HV2903 ANALOG SWITCH EVALUATION BOARD POWER-UP
AND POWER-DOWN SEQUENCES
Step Power-Up Description Step Power-Down Description
1 V
SS
on 1 V
PP
and V
NN
off
2 V
DD
on 2 V
GP
off
3 V
LL
on with logic signal low 3 V
LL
off with logic signal low
4 V
GP
on 4 V
DD
off
5 V
PP
and V
NN
on 5 V
SS
off
WARNING
Powering HV2903 Evaluation Board up/down in an arbitrary sequence may cause
damage to the device.
TABLE 2-3: J2 CONTROL INTERFACE SIGNALS
PIN # Name Test Point I/O Type Signal Discretion
J2-A2 SCK — LVCMOS-2.5V Input EEPROM Serial Clock Input
J2-B2 CSB — LVCMOS-2.5V Input EEPROM Chip Select Input
J2-A3 MISO — LVCMOS-2.5V Output EEPROM Serial Data Output
J2-B3 MOSI — LVCMOS-2.5V Input EEPROM Serial Data input
J2-A5 CLR TP15 LVCMOS-3.3V Input HV2903 Latch Clear Logic Input
J2-B5 CLK TP14 LVCMOS-3.3V Input HV2903 Clock Logic Input
J2-C5 LE/EN TP12 LVCMOS-3.3V Input HV2903 Latch Enable Logic Input
J2-D5 MODE TP13 LVCMOS-3.3V Input HV2903 Mode Logic Input
J2-A6 DIN/AB TP20 LVCMOS-3.3V Input HV2903 Data In Logic Input
J2-B6 STBY TP21 LVCMOS-3.3V Input HV2903 Standby Logic Input, Low active
J2-C6 1_A TP11 LVCMOS-3.3V Input Ch1 Pulser input for NMOS to V
NN
J2-D6 1_B TP10 LVCMOS-3.3V Input Ch1 Pulser input for PMOS to V
PP
J2-A7 1_DMP TP9 LVCMOS-3.3V Input Ch1 Pulser Damp Input for PMOS/NMOS to GND
J2-B7 2_A TP19 LVCMOS-3.3V Input Ch2 Pulser input for NMOS to V
NN
J2-C7 2_B TP18 LVCMOS-3.3V Input Ch2 Pulser input for PMOS to V
PP
J2-D7 2_DMP TP17 LVCMOS-3.3V Input Ch2 Pulser Damp Input for PMOS/NMOS to GND
Note 1: All the pins that are not included in this table are no-connect.