Micrel KSZ8873MML, Руководство пользователя

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KSZ8873MML Evaluation Board User’s Guide
Micrel, Inc. January 11, 2011
Confidential Rev. 1.1
3/11
Table of Contents
1.0
Introduction ............................................................................ 4
2.0 Board Features....................................................................... 4
3.0 Evaluation Kit Contents......................................................... 4
4.0 Hardware Description ............................................................ 4
4.1 Strap In Mode .......................................................................................................... 5
4.1.1 Feature Setting Jumpers........................................................................... 6
4.2 I2C Master (EEPROM) Mode .................................................................................. 7
4.3 SPI Slave Mode ....................................................................................................... 8
4.4 10/100 Ethernet PHY Ports..................................................................................... 9
4.5 LED Indicators......................................................................................................... 9
4.6 MII Port Configuration ............................................................................................ 9
5.0 Reference Documents ......................................................... 10
List of Tables
Table 1: Feature Setting Jumpers .................................................................................................. 6
Table 2: Reserved Jumpers ............................................................................................................ 7
Table 3: LED Modes ....................................................................................................................... 9
Table 4: MII Mode Settings............................................................................................................. 9
List of Figures
Figure 1: KSZ8873MML Evaluation Board Block Diagram ............................................................ 5