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MFJ-4416C Super Battery Booster
Instruction and Technical Manual
Version 0A
11
Input Filtering:
The input filter consists of C13 which provides EMI filtering followed by L1,
C12 and C11 which are a low pass filter at the alternator which range. C8, C9 and C10 provide
low ESR energy storage which helps to suppress input noise while providing energy during input
low voltage transient periods. Diode D1 and capacitors C3 and C4 provide additional filtering
and energy storage feeding the SMPS controller IC1. The additional energy storage is isolated
from any transient load causing a voltage drop on the input protecting IC1 from resets and gaps
in the boost function. Diode D2 is a transient suppressor diode and acts to protect the unit against
transient voltages greater than 15 Volts.
SMPS controller:
IC1 is a packaged SMPS controller with built in voltage reference. This is a
constant frequency pule width modulated regulator with built in driver for the MOSFET gates.
The switching frequency is set as 50Khz. The controller is enabled/disabled by the soft start
control input. This input is grounded to disable the SMPS boost supply. An open collector of Q8
and series resistor R44 provide the control function. Feedback from the output voltage is
provided by the voltage divider consisting of R9, Potentiometer R8 and R10. This feedback is
compared against the voltage reference to adjust the pulse width and resulting voltage output.
The voltage reference is supplied to the analog control section for voltage level decision making.
MOSFET drivers and transformer:
A push pull configuration using two FDP56N06
MOSFETs drives the transformer T1. T1 uses two tapped windings allowing the input voltage to
be placed in series with the SMPS output voltage. The turns ration is .57:1 in series with the DC
input voltage results in a boost of 1.57 over the input voltage. The tapped points on the two
windings are fed to the common cathode rectifier pair D3. Using MOSFET Q1 as an example for
both the Q1 and Q2 circuitry. The gate circuit consists of R6, R3 and FB1. R6 and FB1 minimize
ringing and parasitic oscillations while R3 is a base drain that discharges the gate to substrate
capacity while the unit is not powered. The storage of energy in the gate capacity as a result of
residual energy from previous operation or static can allow both transistors to attempt to conduct
during the next power up cycle before the control IC takes control of the gate usually destroying
one or both MOSFETs.
Output Filtering:
The output filter consists of toroid inductor L2 with capacitors C14 through
C22 that act as a low pass filter and energy storage bank. The total energy storage is 23,500 UF
distributed over 5 capacitors to minimize ESR. Capacitor C22 is located close to the output and
serves as an EMI suppressor. Diode D4 is a 15 volt transient suppressor diode and protects the
unit from transient seen on the output terminals.
Over-voltage Protection:
SCR T2 provides a overvoltage crowbar which is controlled by zener
diode D5. The input circuitry uses a pi filter consisting of C25, L3 and C24. This filter minimizes
the false tripping of the OVP circuit by RF energy radiated back into the power leads. R12
protects the gate of the SCR against high currents and C23 and R11 provide time delay and
protects against leakage currents through D5 tripping the OVP.
Enable Circuitry:
The SMPS boost circuit is controlled by grounding its “Soft Start” input. This
is done with an open collector transistor circuit Q8 and series resistor R44. When Q8 is saturated
the soft start input is held at ground and the SMPS boost is inoperative. The circuitry of Q8
provides an OR gate that allows either the enable line or the low voltage disable line to
independently shut off the SMPS boost circuit. The enable line is puller up to the DC input
voltage by R13 and maybe grounded by Q7, SW1 or through pin 3 of the external control
connector. The green LED is illuminated by the grounding of the enable line.
Содержание MFJ-4416C
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