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7I92        30

REFERENCE INFORMATION

LBP16 

SPACE 4 LBP TIMER/UTILITY AREA

Address  space  4  is  for  read/write  access  to  LBP  specific  timing  registers.  All

memory space 4 access is 16 bit. 

Space 4 read with address 

NN51LLHH

Space 4 write with address 

NND1LLHHDDDD

Space 4 read 

NN11

Space 4 write 

NN91DDDD

MEMORY SPACE 4 LAYOUT: 
ADDRESS

DATA

0000 

uSTimeStampReg

0002 

WaituSReg

0004 

HM2Timeout 

0006 

WaitForHM2RefTime

0008 

WaitForHM2Timer1

000A 

WaitForHM2Timer2

000C 

WaitForHM2Timer3

000E 

WaitForHM2Timer4

0010..001E Scratch registers for any use

The uSTimeStamp register reads the free running hardware microsecond timer. It

is useful for timing internal 7I92 operations. Writes to the uSTimeStamp register are a no-
op. The WaituS register delays processing for the specified number of microseconds when
written, (0 to 65535 uS) reads return the last wait time written. The HM2TimeOut register
sets the timeout value for all WaitForHM2 times (0 to 65536 uS).

All the WaitForHM2Timer registers wait for the rising edge of the specified timer or

reference output when read or written, write data is don’t care, and reads return the wait
time in uS. The HM2TimeOut register places an upper bound on how long the WaitForHM2
operations will wait. HM2Timeouts set the HM2TImeout error bit in the error register.

Содержание 7i92

Страница 1: ...7I92 ETHERNET ANYTHING I O MANUAL Version 1 7...

Страница 2: ...This page intentionally not blank...

Страница 3: ...ADDRESS SELECTION 3 CONNECTORS 4 CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS 4 7I92 I O CONNECTOR PIN OUT 5 POWER CONNECTOR PIN OUT 7 JTAG CONNECTOR PIN OUT 7 OPERATION 8 FPGA 8 FPGA PINOUT 8 IP...

Страница 4: ...PERATION 8 MESAFLASH 12 SETTING EEPROM IP ADDRESS 12 FREE EEPROM SPACE 13 FALLBACK INDICATION 13 FAILURE TO CONFIGURE 13 CLOCK SIGNALS 13 LEDS 14 PULLUP RESISTORS 14 I O LEVELS 14 STARTUP I O VOLTAGE...

Страница 5: ...ANGES FORMAT 20 INFO AREA ACCESS 21 7I92 SUPPORTED MEMORY SPACES 22 SPACE0 HOSTMOT2 REGISTERS 22 SPACE1 ETHERNET CHIP ACCESS 24 SPACE2 ETHERNET EEPROM CHIP ACCESS 24 ETHERNET EEPROM LAYOUT 25 SPACE3 F...

Страница 6: ...e encoder counting PWM generation digital I O Smart Serial remote I O BISS SSI SPI UART interfaces and more Configurations are available that are compatible with common breakout cards and multi axis s...

Страница 7: ...s disabled DB25 pins 22 through 25 are grounded Jumper W3 sets the power option on header P1 and W4 sets the power option on DB25 connector P2 JUMPER POS FUNCTION W3 W4 UP BREAKOUT POWER ENABLED W3 W4...

Страница 8: ...P address These options are selected by Jumpers W5 and W6 W5 W6 IP ADDRESS DOWN DOWN FIXED 192 168 1 121 DEFAULT DOWN UP FIXED FROM EEPROM UP DOWN BOOTP UP UP INVALID Note that the initial EEPROM IP a...

Страница 9: ...7I92 4 CONNECTORS CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS...

Страница 10: ...r 7I92 IO P2 connector pinouts are as follows P2 FIRST I O CONNECTOR PINOUT DB25 PIN HDR PIN FUNCTION DB25 PIN HDR PIN FUNCTION 1 1 IO0 14 2 IO1 2 3 IO2 15 4 IO3 3 5 IO4 16 6 IO5 4 7 IO6 17 8 IO7 5 9...

Страница 11: ...12 GND 13 IO27 14 GND 15 IO28 16 GND 17 IO29 18 GND or 5V 19 IO30 20 GND or 5V 21 IO31 22 GND or 5V 23 IO32 24 GND or 5V 25 IO33 26 GND or 5V Note 26 pin header P1 will match standard parallel port p...

Страница 12: ...OP SQUARE PAD 2 GND BOTTOM ROUND PAD JTAG CONNECTOR PINOUT P4 is a JTAG programming connector This is normally used only for debugging or if both EEPROM configurations have been corrupted In case of c...

Страница 13: ...a standard network with standard tools for non real time applications No fragmentation is allowed so maximum packet size is 1500 bytes UDP All 7I92 data communication is done via UDP packets The 7I92...

Страница 14: ...s that Ethernet access will not be possible For this reason there is a backup method to recover from FPGA boot failures fallback FALLBACK The 7I92 flash memory normally contains two configuration file...

Страница 15: ...ayout is as follows The first half of M25P16 sector layout is as follows 0x00000 BOOT BLOCK 0x10000 FALLBACK CONFIGURATION BLOCK 0 0x20000 FALLBACK CONFIGURATION BLOCK 1 0x30000 FALLBACK CONFIGURATION...

Страница 16: ...1 0x120000 USER CONFIGURATION BLOCK 2 0x130000 USER CONFIGURATION BLOCK 3 0x140000 USER CONFIGURATION BLOCK 4 0x150000 USER CONFIGURATION BLOCK 5 0x160000 UNUSED FREE 0x170000 UNUSED FREE 0x180000 UNU...

Страница 17: ...nabled If multiboot FPGA files are loaded they will likely cause a configuration failure If mesaflash is run with a Bhelp command line argument it will print usage information The following examples a...

Страница 18: ...is can be fixed by running the configuration utility and re writing the user configuration FAILURE TO CONFIGURE The 7I92 should configure its FPGA within a fraction of a second of power application If...

Страница 19: ...on the 7I92 have programmable I O levels for interfacing with different logic families The 7I92 does not support use of the I O standards that require input reference voltages All standard Mesa config...

Страница 20: ...on in 3 6 and 10 foot lengths BREAKOUT POWER OPTION When used with Mesa breakout daughter cards the 7I92 can supply up to 1A of 5V power to each of the daughter cards This option is disabled by defaul...

Страница 21: ...daughtercard on P2 and a 7I74 eight channel RS 422 interface on P1 The 7I74 is configured with eight Smart Serial channels G540X2D G540X2 is a configuration intended to work with two Gecko G540 four a...

Страница 22: ...ur axis step dir daughtercard It will support two 7I78 daughtercards one on each of the 7I92s I O connectors The configuration includes eight hardware step generators two PWM generators two encoder in...

Страница 23: ...nter C Indicates if memory space itself C 0 or associated info area for the memory will be accessed C 1 M Is the 3 bit memory space specifier 000b through 111b S Is the transfer element size specifier...

Страница 24: ...t read access is allowed to the info area 0000 COOKIE 0X5A0N WHERE N ADDRESS SPACE 0 7 0002 MEMSIZES 0004 MEMRANGES 0006 ADDRESS POINTER 0008 SPACENAME 0 1 000A SPACENAME 2 3 000C SPACENAME 4 5 000E S...

Страница 25: ...AREA MEMRANGES FORMAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E E E E E P P P P P S S S S S S E Is erase block size P Is Page size S Ps address range Ranges are 2 E 2 P 2 S All sizes and ranges are in...

Страница 26: ...unt increment field of the LBP16 command and the LLHH is the low and high bytes of the address Ispace 0 read with address NN61LLHH HostMot2 space Ispace 0 read NN21 Ispace 1 read with address NN65LLHH...

Страница 27: ...order for convenience In the hex command examples the NN is the count increment field of the LBP16 command and the LLHH is the low and high bytes of the address SPACE 0 HOSTMOT2 REGISTERS This addres...

Страница 28: ...Example write 4 GPIO ports starting at 0x1000 84C20010AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD 84 84 NN 4 Inc bit so address is incremented after each access C2 Write to space 0 with address included after co...

Страница 29: ...register 0145C000 01 NN read 1 16 bit value 45 read space 1 with address included C0 LSB of CIDER address 00 MSB of CIDER address SPACE 2 ETHERNET EEPROM CHIP ACCESS This space is used to store the Et...

Страница 30: ...ons a LBP16 read operation should follow the write s for host synchronization Example write EEPROM IP address with 192 168 0 32 C0 A8 0 20 in hex 01D91A00025A Enable EEPROM area writes 82C920002000A8C...

Страница 31: ...r 8 9 RO 001A CardNameChar 10 11 RO 001C CardNameChar 12 13 RO 001E CardNameChar 14 15 RO 0020 EEPROM IP address LS word RW 0022 EEPROM IP address MS word RW 0024 EEPROM Netmask LS word RW V16 and fir...

Страница 32: ...nly flash ID register 000C SEC_ERASE 32 bit write only sector erase register Unlike other memory spaces flash memory space is accessed indirectly by writing the address register FL_ADDR and then readi...

Страница 33: ...BP packet 1450 bytes Writes and erases require that the EEPROMWEna be set to 5A03 Note that EEPROMWEna is cleared at the end of every LPB packet so the write EEPROMWEna command needs to prepended to a...

Страница 34: ...sector 0x00010000 01D91A00035A Write EEPROMWEna with 0x5A03 01CE000000000100 Write flash address with 0x 00010000 01CE0C0000000000 Write sector erase command with dummy 32 bit data 0 014E0000 Read fl...

Страница 35: ...imeStamp register reads the free running hardware microsecond timer It is useful for timing internal 7I92 operations Writes to the uSTimeStamp register are a no op The WaituS register delays processin...

Страница 36: ...and TXUDPCount can be used as sequence numbers to verify packet reception and transmission Space 6 read with address NN59LLHH Space 6 write with address NND9LLHHDDDD Space 6 read NN19 Space 6 write NN...

Страница 37: ...ases N is memory space of EEPROM or flash Note that this is cleared at the end of every packet 001C LBPReset Setting this to a non zero value will do a full reset of the LBP16 firmware The 7I92 will r...

Страница 38: ...LAYOUT ADDRESS DATA 0000 CardNameChar 0 1 0002 CardNameChar 2 3 0004 CardNameChar 4 5 0006 CardNameChar 6 7 0008 CardNameChar 8 9 000A CardNameChar 10 11 000C CardNameChar 12 13 000E CardNameChar 14...

Страница 39: ...commands import socket s socket socket socket AF_INET socket SOCK_DGRAM 0 sip 192 168 1 121 sport 27181 s settimeout 2 while 2 0 sdata raw_input sdata sdata decode hex s sendto sdata sip sport try da...

Страница 40: ...ad 5V POWER CONSUMPTION 250 mA No external load MAX 5V CURRENT TO I O CONNS 1000 mA Each PTC Limit TEMPERATURE RANGE C version 0 o C 70 o C TEMPERATURE RANGE I version 40 o C 85 o C INPUT VOLTAGE 5V T...

Страница 41: ...7I92 36 REFERENCE INFORMATION CARD DRAWING...

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