DMU380ZA Series
User’s Manual
________________________________________________________________________
Doc# 7430-3810 Rev. 02
Page 44
Data should be read from the DMU380ZA when the data-ready line is set (see
Section 5.7.1)
SPI Timing
The timing requirements for the SPI the are listed in Table 31 and illustrated in Figure 16
and Figure 17. In addition, the following operational constraints apply to the SPI
communications:
The unit operates with CPOL = 1 (polarity) and CPHA = 1 (phase)
Data is transmitted 16-bits words, Most Significant Bit (MSB) first
Table 31 SPI Timing Requirements
Parameter
Description
Value
Units
f
CLK
SPI clock frequency
2 (max)
MHz
t
DELAY
Time between successive clock cycles (Figure 16)
9 (min)
usec
t
SU,NSS
nSS setup time prior to clocking data (Figure 17)
133
nsec
t
h,NSS
nSS hold time following clock signal (Figure 17)
67
nsec
t
V,MISO
Time after falling edge of previous clock-edge that MISO data-
bit is invalid (Figure 17)
25
nsec
t
SU,MOSI
Data input setup time prior to rising edge of clock (Figure 17)
5
nsec
t
h,MOSI
Data input hold time following rising edge of clock (Figure 17)
4
nsec
nSS
CLK
t
DELAY
Figure 16 Delay Time
t
Reset Delay
nRST held low during
master boot-up sequence
Power-on
of master
nRST pulled low
following power-on
nRST released after
system configured
Set nSS low to read data
when Data-Ready line is set
nSS
DR
nRST
Vcc
Figure 15 Startup Timing
