DMU380ZA Series
User’s Manual
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Doc# 7430-3810 Rev. 02
Page 32
5
DMU380ZA SPI Port Interface Definition
The DMU380ZA provides a SPI interface for data communications. This section of the
user’s
manual defines the DMU380ZA register map, register control capabilities, and the
data register reading and writing methodologies.
The DMU380ZA operates as a slave device. The master device must be configured to
communicate with the DMU380ZA using the following settings:
Data transferred in 16-bit word-length and MSB-first
f
CLK
≤ 2.0 MHz
CPOL = 1 (clock polarity) and CPHA = 1 (clock phase)
Additional operational requirements are described in Section 5.8.
DMU380ZA Register Map
5.1
Table 18 describes the DMU380ZA register map.
Table 18 DMU380ZA Register Map
1
Name
Read/Write Address
Default Function
Reserved
N/A
0x00 to 0x03 N/A
X_RATE
R
0x04
N/A
X-Axis Rate-Sensor Output
Y_RATE
R
0x06
Y-Axis Rate-Sensor Output
Z_RATE
R
0x08
Z-Axis Rate-Sensor Output
X_ACCEL
R
0x0A
N/A
X-Axis Accelerometer Output
Y_ACCEL
R
0x0C
Y-Axis Accelerometer Output
Z_ACCEL
R
0x0E
Z-Axis Accelerometer Output
X_MAG
R
0x10
N/A
X-Axis Magnetometer Output
Y_MAG
R
0x12
Y-Axis Magnetometer Output
Z_MAG
R
0x14
Z-Axis Magnetometer Output
RATE_TEMP
R
0x16
N/A
Rate-sensor temperature
BOARD_TEMP
R
0x18
N/A
Board temperature
Reserved
R
0x1A to 0x33 N/A
SELF_TEST
2
R/W
0x34/0x35
0x00
See Table 25: Initiate Self-Test / Configure Data-Ready
output signal
DATA_READY
R/W
0x35/0x34
0x04
OUTPUT_DATA_RATE
R/W
0x36/0x37
0x01
See Table 26: Set Output Data Rate (ODR) / Select the
system clock (internal/external)
3
SYSTEM_CLOCK
R/W
0x37/0x36
0x01
RS_DYNAMIC_RANGE
R/W
0x38/0x39
0x02
See Table 27: Set rate-sensor dynamic range (SPI only) /
1
Register and data-packet availability is based on the features of the DMU380ZA (see Table 2).
2
Register reads are performed 2-bytes at a time while writes are a single byte in length. In operation, the
SELF_TEST/DATA_READY register should be read together starting at register 0x34. This applies to other shared
registers as well.
3
If an external sync pulse is applied, then the system cannot return to internal timing without resetting the system and
removing the sync signal.