8
MAX3421E Programming Guide
Accessing the MAX3421E Registers
An SPI master controls the MAX3421E by writing and reading 21 internal registers, R0 through
R20. The SPI master begins every register access by asserting the MAX3421E SS# (slave select,
active low) pin, and clocking in eight bits that comprise the SPI command byte.
shows
the command byte format.
ACKSTAT
DIR
1=wr 0=rd
0
Reg0
Reg1
Reg2
Reg3
Reg4
b7
b6
b5
b4
b3
b2
b1
b0
Figure 1. SPI command byte. As for all SPI transfers, bit 7 is sent first. The ACKSTAT bit is
valid only in peripheral mode; the MAX3421E ignores it in host mode.
Reg4:Reg0 set the register address, with valid values 0 to 31. The MAX3421E ignores Reg
values above 31. The direction bit sets the direction for subsequent bytes in the transfer. The
ACKSTAT bit duplicates a USB control bit (R9 bit 6), and is valid only when the MAX3421E
operates as a USB peripheral. The SIE ignores the ACKSTAT bit when HOST = 1.
After sending the command byte, the SPI master transfers one or more bytes in the direction
indicated by the DIR bit. Keeping SS# low, the SPI master provides additional bursts of eight
SCK pulses for each byte. When the byte transfers are complete, the SPI master de-asserts SS#
(drives high) and the transfer terminates.
The MAX3421E has two register types, FIFOS and control registers. Repeated reads or writes to
a register have different effects, depending on the register type.
Registers R1, R2, and R4 access internal FIFOS. After selecting the register number with the
command byte, the SPI master loads or unloads consecutive FIFO bytes by repeating reads or
writes during the same SPI transfer (maintaining SS# low). To write 45 bytes into the
SENDFIFO, for example, the SPI master would perform the following steps:
1. Set SS# = 0 to start the transfer.
2. Issue eight SCLK pulses and send the command byte 00010010. This command byte
selects R2 (SNDFIFO) for a write operation (DIR = 1).
3. Issue eight SCK pulses, each clocking a data bit into the SNDFIFO register, one bit per
SCK rising edge. Every byte the SIE writes the FIFO byte and advances an internal FIFO
address pointer.
4. Repeat Step 3 for 44 more times, clocking in a total of 45 bytes into the SNDFIFO.
5. Set SS# = 1 to terminate the transfer.
Registers R13 through R31 are MAX3421E control registers. If the SPI master repeatedly reads
or writes R13 through R20 during the same SPI transfer (SS# low), every byte read or write
automatically increments the internal register address. This action allows reading or writing
consecutive registers without writing a new command byte to set each new register address. The
register address continues to increment in this manner until R20 is reached, at which point the