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Maxim MAX12557, Технические характеристики, Страница: 6 / 28

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MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

6

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C

L

≈

10pF at digital outputs, V

IN

= -0.5dBFS (differen-

tial), DIFFCLK/

SECLK

= OV

DD

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/

T

= GND, f

CLK

= 65MHz, T

A

= -40°C to

+85°C, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

D 0A–D 13A, D O RA,
D 0B–D 13B and  D ORB Tr i - S tate
O utp ut C ap aci tance ( N ote 3) 

C

OUT

3

pF

DAV Tri-State Output
Capacitance (Note 3)

C

DAV

6

pF

POWER REQUIREMENTS

Analog Supply Voltage

V

DD

3.15

3.30

3.60

V

Digital Output Supply Voltage

OV

DD

1.70

2.0

V

DD

V

Normal operating mode
f

IN

 = 175MHz at -0.5dBFS,

single-ended clock
(DIFFCLK/

SECLK

 = GND)

185

Normal operating mode
f

IN

 = 175MHz at -0.5dBFS

differential clock
(DIFFCLK/

SECLK

 = OV

DD

)

193

210

Analog Supply Current

I

VDD

Power-down mode (PD = OV

DD

)

clock idle

0.05

mA

Normal operating mode
f

IN

 = 175MHz at -0.5dBFS

single-ended clock
(DIFFCLK/

SECLK

 = GND)

610

Normal operating mode
f

IN

 = 175MHz at -0.5dBFS

differential clock
(DIFFCLK/

SECLK

 = OV

DD

)

637

693

Analog Power Dissipation

P

VDD

Power-down mode (PD = OV

DD

)

clock idle

0.165

mW

Normal operating mode
f

IN

 = 175MHz at -0.5dBFS

21.3

Digital Output Supply Current

I

OVDD

Power-down mode (PD = OV

DD

)

clock idle

0.001

mA

Содержание MAX12557

Страница 1: ...accepts a 1 7V to 3 6V voltage for flexible interfac ing with various logic levels The MAX12557 is available in a 10mm x 10mm x 0 8mm 68 pin thin QFN package with exposed paddle EP and is specified f...

Страница 2: ...COMB to GND 0 3V to the lower of VDD 0 3V and 3 6V DIFFCLK SECLK G T PD SHREF DIV2 DIV4 to GND 0 3V to the lower of VDD 0 3V and 3 6V D0A D13A D0B D13B DAV DORA DORB to GND 0 3V to OVDD 0 3V Continuo...

Страница 3: ...3 84 5 74 5 fIN 32 5MHz at 0 5dBFS 80 7 fIN 70MHz at 0 5dBFS 81 7 Total Harmonic Distortion THD fIN 175MHz at 0 5dBFS 78 3 dBc fIN 3MHz at 0 5dBFS 89 5 fIN 32 5MHz at 0 5dBFS 84 2 fIN 70MHz at 0 5dBF...

Страница 4: ...oefficient TCREF 50 ppm C Short to VDD sinking 0 24 REFOUT Short Circuit Current Short to GND sourcing 2 1 mA BUFFERED REFERENCE MODE REFIN is driven by REFOUT or an external 2 048V single ended refer...

Страница 5: ...Ended Input High Threshold VIH DIFFCLK SECLK GND CLKN GND 0 8 x VDD V Single Ended Input Low Threshold VIL DIFFCLK SECLK GND CLKN GND 0 2 x VDD V Minimum Differential Clock Input Voltage Swing DIFFCL...

Страница 6: ...utput Capacitance Note 3 CDAV 6 pF POWER REQUIREMENTS Analog Supply Voltage VDD 3 15 3 30 3 60 V Digital Output Supply Voltage OVDD 1 70 2 0 VDD V Normal operating mode fIN 175MHz at 0 5dBFS single en...

Страница 7: ...intermodulation distortion measured with respect to a single carrier amplitude and not the peak to average input power of both input tones Note 5 During power down D0A D13A D0B D13B DORA DORB and DAV...

Страница 8: ...NAD SNR 35 55 45 75 65 85 95 55 45 40 35 50 30 25 20 15 10 5 0 MAX12557 toc12 AIN dBFS THD SFDR dBc THD SFDR vs ANALOG INPUT AMPLITUDE fCLK 65 00352MHz fIN 70MHz THD SFDR FFT PLOT 32 768 POINT DATA RE...

Страница 9: ...0 20 35 40 25 30 45 50 55 60 65 SNR SINAD vs CLOCK SPEED fIN 175MHz AIN 0 5dBFS MAX12557 toc17 fCLK MHz SNR SINAD dB SNR SINAD 60 70 75 80 85 90 20 35 40 25 30 45 50 55 60 65 THD SFDR vs CLOCK SPEED f...

Страница 10: ...fCLK 65 00352MHz fIN 175MHz MAX12557 toc26 OVDD V THD SFDR dBc SFDR THD 3 6 0 200 100 500 400 300 800 700 600 900 3 0 3 2 3 1 3 3 3 4 3 5 3 6 PDISS IVDD ANALOG vs ANALOG SUPPLY VOLTAGE fCLK 65 00352MH...

Страница 11: ...RATURE fIN 175MHz AIN 0 5dBFS MAX12557 toc32 TEMPERATURE C THD SFDR dBc SFDR THD 3 1 2 1 0 2 3 40 10 15 35 60 85 GAIN ERROR vs TEMPERATURE MAX12557 toc33 TEMPERATURE C GAIN ERROR FSR 0 3 0 2 0 1 0 0 1...

Страница 12: ...a 0 1 F capacitor to GND Connect a 10 F and a 1 F bypass capacitor between REFBP and REFBN Place the 1 F REFBP to REFBN capacitor as close to the device as possible on the same side of the PC board 12...

Страница 13: ...Data Valid Digital Output The rising edge of DAV indicates that data is present on the digital outputs The MAX12557 evaluation kit utilizes DAV to latch data into any external back end digital logic...

Страница 14: ...sure that VREFAP VREFBP Similarly when sharing the reference externally connect REFAN to REFBN together to ensure that VREFAN VREFBN 67 REFOUT Internal Reference Voltage Output The REFOUT output volta...

Страница 15: ...OVDD DAV OUTPUT DRIVERS DORA CLOCK DIVIDER DATA FORMAT 14 BIT PIPELINE ADC DIGITAL ERROR CORRECTION OUTPUT DRIVERS DATA FORMAT DIV2 DIV4 INBN D0B TO D13B DORB CHANNEL B REFERENCE SYSTEM COMB REFBN REF...

Страница 16: ...of 2 048V 1 at the REFOUT pin with a 50ppm C temperature coefficient Connect an external 0 1 F bypass capacitor from REFOUT to GND for stability REFOUT sources up to 1mA and sinks up to 0 1mA for exte...

Страница 17: ...The clock duty cycle equalizer uses a delay locked loop DLL to create internal timing signals that are duty cycle independent Due to this DLL the MAX12557 requires approximately 100 clock cycles to ac...

Страница 18: ...PD OVDD DAV enters its high impedance state 10ns after the rising edge of PD and becomes active again 10ns after PD transitions low DAV is capable of sinking and sourcing 600 A and has three times th...

Страница 19: ...e 6 and Figure 7 define the relationship between the digital output and the analog input Gray Code G T 1 VIN_P VIN_N 2 3 x VREF_P VREF_N x 2 x CODE10 8192 16 384 Two s Complement G T 0 VIN_P VIN_N 2 3...

Страница 20: ...tal supply current reduces to 1 A The following list shows the state of the analog inputs and digital out puts in power down mode 1 INAP B INAN B analog inputs are disconnected from the internal input...

Страница 21: ...ATION BINARYX BINARYX 1 BIT POSITION BINARY12 BINARY13 GRAY12 BINARY12 0 1 BINARY12 1 3 REPEAT STEP 2 UNTIL COMPLETE 4 THE FINAL BINARY CONVERSION IS 0 1 0 0 1 1 1 0 1 0 1 0 BINARY GRAY CODE BIT POSIT...

Страница 22: ...signals beyond the Nyquist frequency A set of 75 and 113 termination resistors provide an equivalent 50 termination to the signal source The second set of termination resistors connects to COM_ provid...

Страница 23: ...ltiple ADCs The unbuffered external reference mode allows for pre cise control over the MAX12557 reference and allows multiple converters to use a common reference Connecting REFIN to GND disables the...

Страница 24: ...removes any concern regarding power supply sequencing when powering up or down Grounding Bypassing and Board Layout The MAX12557 requires high speed board layout design techniques Refer to the MAX125...

Страница 25: ...occurs at 0 5 LSB above mid scale The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point Gain Error Gain error is a figure...

Страница 26: ...2 x fIN2 fIN1 Aperture Jitter Figure 14 shows the aperture jitter tAJ which is the sample to sample variation in the aperture delay Aperture Delay Aperture delay tAD is the time defined between the ri...

Страница 27: ...as offset matching MAX12557 Dual 65Msps 14 Bit IF Baseband ADC ______________________________________________________________________________________ 27 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43...

Страница 28: ..._____________Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products Inc Packa...

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