DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
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PERIPHERAL OVERVIEW
The DS87C530/DS83C530 provide several of the most commonly needed peripheral functions in
microcomputer-based systems. These new functions include a second serial port, power-fail reset, Power-
fail interrupt, and a programmable watchdog timer. These are described below, and more details are
available in the
High-Speed Microcontroller User’s Guide
.
SERIAL PORTS
The DS87C530/DS83C530 provide a serial port (UART) that is identical to the 80C52. In addition it
includes a second hardware serial port that is a full duplicate of the standard one. This port optionally
uses pins P1.2 (RXD1) and P1.3 (TXD1). It has duplicate control functions included in new SFR
locations.
Both ports can operate simultaneously but can be at different baud rates or even in different modes. The
second serial port has similar control registers (SCON1; C0h, SBUF1; C1h) to the original. The new
serial port can only use Timer 1 for timer-generated baud rates.
TIMER RATE CONTROL
There is one important difference between the DS87C530/DS83C530 and 8051 regarding timers. The
original 8051 used 12 clocks per cycle for timers as well as for machine cycles. The
DS87C530/DS83C530 architecture normally uses 4 clocks per machine cycle. However, in the area of
timers and serial ports, the DS87C530/DS83C530 will default to 12 clocks per cycle on reset. This allows
existing code with real-time dependencies such as baud rates to operate properly.
If an application needs higher speed timers or serial baud rates, the user can select individual timers to run
at the 4-clock rate. The Clock Control register (CKCON; 8Eh) determines these timer speeds. When the
relevant CKCON bit is logic 1, the DS87C530/DS83C530 use 4 clocks per cycle to generate timer
speeds. When the bit is a 0, the DS87C530 uses 12 clocks for timer speeds. The reset condition is a 0.
CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0.
Unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls are
independent.
POWER-FAIL RESET
The DS87C530/DS83C530 use a precision bandgap voltage reference to decide if V
CC
is out of tolerance.
While powering up, the internal monitor circuit maintains a reset state until V
CC
rises above the V
RST
level. Once above this level, the monitor enables the crystal oscillator and counts 65,536 clocks. It then
exits the reset state. This power-on reset (POR) interval allows time for the oscillator to stabilize.
A system needs no external components to generate a power-related reset. Anytime V
CC
drops below
V
RST
, as in power failure or a power drop, the monitor will generate and hold a reset. It occurs
automatically, needing no action from the software. Refer to the
Electrical Specifications
section for the
exact value of V
RST
.
POWER-FAIL INTERRUPT
The voltage reference that sets a precise reset threshold also generates an optional early warning power-
fail interrupt (PFI). When enabled by software, the processor will vector to program memory address
0033h if V
CC
drops below V
PFW
. PFI has the highest priority. The PFI enable is in the Watchdog Control
SFR (WDCON–D8h). Setting WDCON.5 to logic 1 will enable the PFI. Application software can also
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