Maxim Integrated MAX32660, Руководство пользователя

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MAX32660 User Guide
Maxim Integrated Page 72 of 195
In addition, each channel has a set of reload registers, shown in Table 7-2 , that are used to chain DMA buffers when a
count-to-zero (CTZ) condition occurs.
Table 7-2: Channel Reload Registers
Register Description
DMAn_DST_RLD Destination reload register
DMAn_SRC_RLD Source reload register
DMAn_CNT_RLD Count reload register
Using these eight registers provides each channel with the following features:
•
Full 32-bit source and destination addresses with 24-bit (16 Mbytes) address increment capability
•
Up to 16 Mbytes for each DMA buffer
•
Programmable burst size
•
Programmable priority
•
Interrupt upon CTZ
•
Abort on error
7.2 DMA Channel Arbitration and DMA Bursts
DMAC contains an internal arbiter that allows enabled channels to access the AHB and move data. A DMA channel is
enabled using the
DMAn_CFG .chen bit.
When disabling a channel, poll the DMAn_STAT .ch_st bit to determine if the channel is truly disabled. In general,
DMAn_STAT .ch_st follows the setting of the DMAn_CFG .chen bit. However, the DMAn_STAT .ch_st bit is automatically
cleared under the following conditions:
•
Bus error (cleared immediately)
•
CTZ when the DMAn_CFG . rlden = 0 (cleared at the end of the AHB R/W burst)
•
DMAn_STAT . chen bit transitions to 0 (cleared at the end of the AHB R/W burst)
Whenever the DMAn_STAT .ch_st bit transitions from 1 to 0, the corresponding DMAn_CFG .chen bit is also cleared. During
an AHB read/write burst, attempting to disable an active channel is delayed until burst completion.
Once a channel is programmed and enabled, it generates a request to the arbiter immediately (for
memory-to-memory DMA) or whenever its associated peripheral requests DMA (for memory-to-peripheral or peripheral-
to-memory DMA).
The arbiter grants requests to a single channel at a time. Granting is done based on priority — a higher priority request is
always granted. Within a given priority level, requests are granted on a round-robin basis.
Wh n a chann l’s r qu st is grant , it runs a transf r. nc th transf r c mpl t s, th chann l r linquish s its
grant.
Only an error condition can interrupt an ongoing data transfer.
DMAn_CFG .reqsel determines which request is used to initiate a DMA burst. In the case of a memory-to-memory transfer,
the channel is treated as always requesting DMA access. The DMAn_CFG .priority field determines the DMA channel priority.