Maxim Integrated MAX32600, Руководство пользователя

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MAX32600 User’s Guide Analog Front End 8.3 ADC
The Track portion of the acquisition window is controlled via the ADC_TG_CTRL0.pga_trk_cnt register field, and the Hold portion is controlled by the ADC_TG_CT
−
RL1.pga_acq_cnt field. Refer to Sample Rate Calculation for details.
When the ADC is operating in bipolar signal conditioning mode, PGA gain can be used in conjunction with the default ADC input range V
REF
/2 ( ADC_CTRL0.range =
0). This can provided a total effective gain of 16X. Although both PGA and ADC can provide a 2X gain (in bipolar mode), for optimal SNR, the PGA should be used.
Advanced Details
The PGA is a track and hold input device with switched-capacitance architecture. This architecture enables minimal offset and gain errors, rail-to-rail inputs, and
high input impedance. It is important that the input signal source to the PGA be capable of fully settling within the track portion of the measurement. To achieve the
settling time requirements as the sample rate increases, the source output impedance needs to be low. The sampling capacitance increases with gain as shown in
the table below.
Gain Input Capacitance (typical)
1X 7pF
2X 13pF
4X 25pF
8X 49pF
The PGA input capacitance should be modeled as a fully discharged capacitor that is periodically connected to the input signal during each track point of the
measurement window. The input signal must be capable of charging and settling the PGA input capacitor with an accuracy of
V
REFADC
2
N
(with N being the required ADC
measurement resolution) to fully settle. For an RC network, this settling time is:
t
SET T LING
=
ln
(
RC
×
2
N
)
The output impedance of the signal source must be carefully considered and balanced with the PGA track window time (or the ADC acquisition time if the PGA is
bypassed) to meet the settling time.
Input Voltage to the Receive Path
The choices of ADC, PGA, and reference voltage affect the full scale input voltage to the receive path. The table below illustrates these interactions.
ADC Mode ADC Range Input Mode V
I
PGA Mode ( Gain , Bypass ) Min V
I
Max V
I
Notes
Unipolar Not Applicable Single-Ended Ai 1X (Bypass) 0 V
REF
Rev.1.3 April 2015 Maxim Integrated Page 416