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writes are not buffered and the CPU must wait until the write is complete be-
fore starting another write cycle.
PCI Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction (Enabled)
The mainboard’s chipset has an embedded 32-bit post write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
Memory Hole (Disabled)
This item is used to reserve memory space for ISA expansion cards that re-
quire it.
System BIOS/Video RAM Cacheable (Disabled)
These items allow the video and system to be cached in memory for faster
execution. Leave these items at the default value for better performance.
Memory Parity/ECC Check (Disabled)
Enable this item to allow BIOS to perform a parity check to the POST memory
tests. Select Enabled only if the system DRAM supports parity checking.
Press <Esc> to return to the previous screen.
Integrated Peripherals Option
These options display items that define the operation of peripheral compo-
nents on the system's input/output ports.
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
Integrated Peripherals
Item Help
VIA OnChip IDE Device
[Press Enter]
VIA On Chip PCI Device
[Press Enter]
Super I/O Device
[Press Enter]
Init Display First
[PCI Slot]
OnChip USB Controller
[All Enabled]
USB Keyboard Support
[Disabled]
USB Mouse Support [Disabled]
IDE HDD Block Mode
[Enabled]
Menu Level
↑↑↑↑
↓↓↓↓
→
→
→
→
←
←
←
←
: Move
Enter : Select
+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults
