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CPU to PCI Write Buffer
Default: Enabled
When enabled, up to four words of data can be written to the PCI bus
without interrupting the CPU. When disabled, a write buffer is not used
and the CPU read cycle will not be completed until the PCI bus signals
that it is ready to receive the data.
PCI Dynamic Bursting
Default: Enabled
When set to Enabled, every write transaction goes to the write buffer.
Burstable transactions then “burst” on the PCI bus and nonburstable
transaction do not.
PCI Master 0 WS Write
Default: Enabled
When set to Enabled, writes to the PCI bus are executed with zero wait
states.
PCI Delay Transaction
Default: Enabled
The chipset has an embedded 32-bit posted write buffer to support de-
lay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
PCI#2 Access #1 Retry
Default: Enabled
When set to Enabled, the AGP Bus (PCI#2) access to PCI Bus (PCI#1)
is executed with the error retry feature.
AGP Master 1 WS Write
Default: Disabled
This implements a single delay when writing to the AGP Bus. By default,
two-wait states are used by the system, allowing for greater stability.
AGP Master 1 WS Read
Default: Disabled
This implements a single delay when reading to the AGP Bus. By de-
fault, two-wait states are used by the system, allowing for greater
stability.
USB Keyboard Support
Default: Disabled
Enable this item if you plan to use a keyboard connected through the
USB port in a legacy operating system (such as DOS) that does not
support Plug and Play.
OnChip Sound
Default: Auto
When set to Disabled, the onboard audio chip is turned off.
