10
Signal Type
+5 V TTL compatible
Logic level Low
< 0.4 V while sinking 4mA
Logic level high
Between 2.4 VDC and 5 VDC
Output while sourcing 200uA
High state output impedance
1K
Ω
from output to common
PWR_OK delay
100 ms < T3 < 500 ms
PWR_OK rise time
T5
≤
10 ms
Power down warning
T4 > 1 ms
3.4.2
PWR_ON
a.
PWR_ON is an active-low, TTL-compatible signal that allows a motherboard to
remotely control the power supply in conjunction with features such as soft on/off,
wake-on-LAN, or wake-on-modem. When PWR_ON is pulled to TTL low, the
power supply should turn on the five main DC output rails: +12VDC, +5VDC,
+3.3VDC, -5VDC, and -12VDC. When PWR_ON is pulled to TTL high or open
circuited, the DC output rails should not deliver current and should be held at zero
potential with respect to ground. PWR_ON has no effect on the +5VSB output,
which is always enabled whenever the AC power is present.
b.
Power supply shall provide an internal pull-up to TTL high. The power supply shall
also provide debounce circuitry on PWR_ON to prevent it from oscillating on/off at
startup due to activation by a mechanical switch. The DC output enable circuitry
must be SELV-compliant.
3.4.3
+5VSB
+5VSB is a "standby" supply output that is active whenever the AC power is present. It
provides a power source for circuits that must remain operational when the five main DC
output rails are in a disabled state. Example uses include soft power control, wake-
onLAN, wake-on-modem, intrusion detection, or suspend state activities. +5VSB is
required for the implementation of PWR_ON.
The +5VSB output should be capable of delivering 2.0A at +5 V
±
5% to external circuits.
3.4.4 Power-on Time
The power-on time is defined as the time from when PWR_ON is pulled low to when the
+5VDC and +3.3VDC outputs are within the regulation ranges specified in Section 3.2.1.
The power-on time shall be less than 500ms. +5VSB shall have a power-on time of 2
seconds maximum after application of valid DC voltages.
3.4.5 Risetime
The output voltages shall rise from <10% of nominal to within the regulation ranges
specified in Section 3.2.1 within 0.1ms to 20ms (0.1ms < T2
≤
20ms).
