85
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
SCF with High Tolerance to Clock Jitter
2nd order Analog LPF
Single Ended Output Buffer
Digital de-emphasis for 32k, 44.1k and 48kHz sampling
Soft mute
Digital Attenuator (Linear 256 steps)
I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I
2
S
Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -94dB
Dynamic Range: 106dB
Power supply: 4.5 to 5.5V
Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
LRCK
BICK
SDTI
Audio
Data
Interface
MCLK
PDN
'6
Modulator
AOUTL
8X
Interpolator
SCF
LPF
AOUTR
VDD
VSS
VCOM
De-emphasis
Control
P/S
μ
P
Interface
Clock
Divider
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
'6
Modulator
8X
Interpolator
DZFR
DZFL
SCF
LPF
ATT
ATT
No. Pin
Name
I/O Function
1
MCLK
I
Master Clock Input Pin
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock Pin
3
SDTI
I
Audio Serial Data Input Pin
4
LRCK
I
L/R Clock Pin
5 PDN
I Power-Down
Mode
Pin
When at “L”, the AK4384 is in the power-down mode and is held in reset.
The AK4384 should always be reset upon power-up.
SMUTE
I
Soft Mute Pin in parallel mode
“H”: Enable, “L”: Disable
6
CSN
I
Chip Select Pin in serial mode
ACKS
I
Auto Setting Mode Pin in parallel mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
7
CCLK
I
Control Data Clock Pin in serial mode
DIF0
I
Audio Data Interface Format Pin in parallel mode
8
CDTI
I
Control Data Input Pin in serial mode
9 P/S
I Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
10
AOUTR
O
Rch Analog Output Pin
11
AOUTL
O
Lch Analog Output Pin
12
VCOM
O
Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1
P
F ceramic capacitor in parallel with a
10
P
F electrolytic cap.
13 VSS
-
Ground
Pin
14 VDD
-
Power
Supply
Pin
15
DZFR
O
Rch Data Zero Input Detect Pin
16
DZFL
O
Lch Data Zero Input Detect Pin
Note: All input pins except pull-up pin should not be left floating.
IC52 :AK4384ET (SR5002/U only)
Содержание SR5002
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