QL09,QZ11:LC74781
QD01/QD02/QD03:AD1855
47
48
Pin
Input/Output
Pin Name
Description
1
I
DGND
Digital Ground.
2
I
MCLK
Master Clock Input. Connect to an external clock source at either 256, 384
or 512 F
S
.
3
I
CLATCH
Latch input for control data. This input is rising-edge sensitive.
4
I
CCLK
Control clock input for control data. Control input data must be valid on the
rising edge of CCLK. CCLK may be continuous or gated.
5
I
CDATA
Serial control input, MSB first, containing 16 bits of unsigned data per
channel. Used for specifying channel specific attenuation and mute.
6
I
384/256
Selects the master clock mode as either 384 times the intended sample fre-
quency (HI) or 256 times the intended sample frequency (LO). The state of
this input should be hardwired to logic HI or logic LO, or may be changed
while the AD1855 is in power-down/reset. It must not be changed while the
AD1855 is operational.
7
I
X2MCLK
Selects internal clock doubler (LO) or internal clock = MCLK (HI).
8
O
ZEROR
Right Channel Zero Flag Output. This pin goes HI when Right Channel has
no signal input for more than 1024 LR Clock Cycles.
9
I
DEEMP
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.
This is used to impose a 50 ms/15 ms response characteristic on the output
audio spectrum at an assumed 44.1 kHz sample rate.
10
I
96/ 48
Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
11, 15
I
AGND
Analog Ground.
12
O
OUTR+
Right Channel Positive line level analog output.
13
O
OUTRÐ
Right Channel Negative line level analog output.
14
O
FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 m F and 0.1 m F capacitors to the AGND.
16
O
OUTLÐ
Left Channel Negative line level analog output.
17
O
OUTL+
Left Channel Positive line level analog output.
18
I
AVDD
Analog Power Supply. Connect to 5 V supply.
19
O
FILTB
Filter Capacitor connection, connect 10 m F capacitor to AGND.
20
I
I DPM1
Input serial data port mode control one. With IDPM0, defines one of four
serial modes.
21
I
I DPM0
Input serial data port mode control zero. With IDPM1, defines one of four
serial modes.
22
O
ZEROL
Left Channel Zero Flag output. This pin goes HI when Left Channel has no
signal input for more than 1024 LR Clock Cycles.
23
I
MUTE
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor-
mal operation.
24
I
PD/RST
Power-Down/Reset. The AD1855 is placed in a low power consumption
mode when this pin is held LO. The AD1855 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values.
Connect HI for normal operation.
25
I
L /RCLK
Left/ Right clock input for input data. Must run continuously.
26
I
BCLK
Bit clock input for input data. Need not run continuously; may be gated or
used in a burst fashion.
27
I
SDATA
Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of
twos complement data per channel.
28
I
DVDD
Digital Power Supply Connect to d5 V supply.
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD1855
FILTR
OUTRÐ
OUTR+
AGND
96/48
DEEMP
ZEROR
DGND
MCLK
CLATCH
CCLK
X2MCLK
384/256
CDATA
AGND
OUTLÐ
OUTL+
AVDD
FILTB
IDPM1
IDPM0
DVDD
SDATA
BCLK
L/RCLK
ZEROL
MUTE
PD/RST
P9
P10
P11
P12
6
7
8
9
14 P1
DATA
CLK
VSS
VDD
STB
CLR
P2
P3
P4
P5
P6
P7
P8
18
12
13
15
16
17
1
2
3
4
10
11
5
CONTROL CIRCUIT
SHIFT REGISTER
LATCH CIRCUIT
NJU3713
QV01:NJU3713
ATTEN/
MUTE
ATTEN/
MUTE
SERIAL
DATA
INTERFACE
83
INTERPOLATOR
MULTIBIT SIGMA-
DELTA MODULATOR
SERIAL CONTROL
INTERFACE
CLOCK
CIRCUIT
OUTPUT
BUFFER
OUTPUT
BUFFER
DAC
DAC
MULTIBIT SIGMA-
DELTA MODULATOR
VOLTAGE
REFERENCE
VOLUME
MUTE
CONTROL DATA
INPUT
3
2
DIGITAL
SUPPLY
CLOCK
IN
96/48F
S
CLOCK
ANALOG
OUTPUTS
2
2
ZERO
FLAG
ANALOG
SUPPLY
DE-EMPHASIS
MUTE
PD/RST
2
SERIAL
MODE
16-/18-/20-/24-BIT
DIGITAL
DATA INPUT
AD1855
83
INTERPOLATOR
3
384/256
X2MCLK
