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QD01 : TMS320VC5416PGE-160
The TMS320VC5416PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are sh
Figure 2–2.
CV HDS1
A18
A17
DVSS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
DVSS
HPIENA
CVDD
CVSS
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
DVSS
DVDD
BDX1
BFSX1
CVSS
A22
CVSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
CVDD
HAS
DVSS
CVSS
CVDD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
CVSS
BDR1
BFSR1
SS
DV
144
A21 CV
143 142 141
A8
140
A7
139
A6
138
A5
137
A4
136
HD6
135
A3
134
A2
133
A1
132
A0
131
DV
130 129 128 127
CV
126 125
HD5
124
D15
123
D14
122
D13
121
HD4
120
D12
11
9
D1
1
11
8
11
7
D9
11
6
D8
11
5
D7
11
4
D6
11
3
11
2
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
SS
CV
BCLKR1
HCNTL0
SS
BCLKR0 BCLKR2
BFSR0 BFSR2
BDR0
HCNTL1
BDR2
BCLKX0 BCLKX2
SS
DD SS
HD0
BDX0 BDX2
IACK
HBIL
NMI
INT0 INT1 INT2 INT3
DD
HD1
SS
HRDY
HINT
111
CV
11
0
A19
109
70 71 72
BCLKX1
SS
DV
D10
BFSX2
SS
A20 DV
DD
CV
HDS2
SS
DV
DV CV
DV DV
CV
CV
DD DD
DD
DD SS
BFSX0
A9
Signal Descriptions
Table 2–2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2–2. Signal Descriptions
TERMINAL
I/O† DESCRIPTION
TERMINAL
NAME
I/O† DESCRIPTION
DATA SIGNALS
A22 (MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(LSB)
I/O/ZठParallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB
lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16
to A22, address external program space memory. A22–A0 is placed in the high-impedance state in the hold
mode. A22–A0 also goes into the high-impedance state when OFF is low.
A17–A0 are inputs in HPI16 mode. These pins can be used to address internal memory via the host-port interface
(HPI) when the HPI16 pin is high. These pins also have Schmitt trigger inputs.
The address bus has a bus holder feature that eliminates passive components and the power dissipation
associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into
a high-impedance state.
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
I/O/Z‡§ Parallel data bus D15 (MSB) through D0 (LSB). D15–D0 is multiplexed to transfer data between the core CPU
and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high). D15–D0 is
placed in the high-impedance state when not outputting data or when RS or HOLD is asserted. D15–D0 also goes
into the high-impedance state when OFF is low. These pins also have Schmitt trigger inputs.
The data bus has a bus holder feature that eliminates passive components and the power dissipation associated
with them. The bus holder keeps the data bus at the previous logic level when the bus goes into the
high-impedance state. The bus holders on the data bus can be enabled/disabled under software control.
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
Table 2–2. Signal Descriptions (Continued)
TERMINAL
NAME
DESCRIPTION I/O†
TERMINAL
NAME
DESCRIPTION I/O†
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
IACK O/Z
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low.
INT0‡
INT1‡
INT2‡
INT3‡
I
External user interrupt inputs. INT0–INT3 are maskable and are prioritized by the interrupt mask register (IMR)
and the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register (IFR).
NMI‡ I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
RS‡
I
Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to
0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects
various registers and status bits.
MP/MC I
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
that is selected at reset.
MULTIPROCESSING SIGNALS
BIO‡ I
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
XF O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low,
and is set high at reset.
MEMORY CONTROL SIGNALS
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
communicating to a particular external space. Active period corresponds to valid address information. DS, PS,
and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance
state when OFF is low.
MSTRB O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
READY I
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
R/W O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the
high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.
IOSTRB O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
HOLD I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the 5416, these lines go into the high-impedance state.
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
Table 2–2. Signal Descriptions (Continued)
TERMINAL
NAME
DESCRIPTION I/O†
TERMINAL
NAME
DESCRIPTION I/O†
MEMORY CONTROL SIGNALS (CONTINUED)
HOLDA O/Z
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and control lines are in the high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when OFF is low.
MSC O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive
high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external
wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF
is low.
IAQ O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus and goes into the high-impedance state when OFF is low.
TIMER SIGNALS
CLKOUT O/Z
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the
machine-cycle rate divided by 4.
CLKMD1‡
CLKMD2‡
CLKMD3‡
I
Clock mode select signals. CLKMD1–CLKMD3 allow the selection and configuration of different clock modes
such as crystal, external clock, and PLL mode. The external CLKMD1–CLKMD3 pins are sampled to determine
the desired clock generation mode while RS is low. Following reset, the clock generation mode can be
reconfigured by writing to the internal clock mode register in software.
X2/CLKIN‡ I
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is
revision-dependent, see Section 3.10 for additional information.)
X1 O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision-dependent, see
Section 3.10 for additional information.)
TOUT O/Z
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
BCLKR0‡
BCLKR1‡
BCLKR2‡
I/O/Z
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following
reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BDR0
BDR1
BDR2
I Serial data receive input
BFSR0
BFSR1
BFSR2
I/O/Z
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured
as an input following reset. The BFSR pulse initiates the receive data process over BDR.
BCLKX0‡
BCLKX1‡
BCLKX2‡
I/O/Z
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when
OFF goes low.
BDX0
BDX1
BDX2
O/Z
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
BFSX0
BFSX1
BFSX2
I/O/Z
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes
into the high-impedance state when OFF is low.
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
Table 2–2. Signal Descriptions (Continued)
TERMINAL
NAME
DESCRIPTION I/O†
TERMINAL
NAME
DESCRIPTION I/O†
TEST PINS
TCKঠI
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,
or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.
TDI¶ I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.
TMS¶ I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TRST# I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
EMU0 I/O/Z
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way
of the IEEE standard 1149.1 scan system.
EMU1/OFF I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is
driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into
the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = low,
EMU0 = high
EMU1/OFF = low
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
Table 2–2. Signal Descriptions (Continued)
TERMINAL
NAME
DESCRIPTION I/O†
TERMINAL
NAME
DESCRIPTION I/O†
HOST-PORT INTERFACE SIGNALS
HD0–HD7‡§ I/O/Z
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to
reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven
by the 5416, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled
at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs.
HCNTL0¶
HCNTL1¶
I
Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs
have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 = 1.
HBIL¶ I
Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup
resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1.
HCSঠI
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
HDS1‡¶
HDS2‡¶
I
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe
inputs have internal pullup resistors that are only enabled when HPIENA = 0.
HASঠI
Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA
register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0.
HR/W¶ I
Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
HRDY O/Z
Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host
when the HPI is ready for the next transfer.
HINT O/Z
Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high
.
HINT
goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1.
HPIENA# I
HPI module select. HPIENA must be tied to DVDD to have HPI selected. If HPIENA is left open or connected to
ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus
has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled
when RS goes high and is ignored until RS goes low again.
HPI16# I HPI16 mode selection
SUPPLY PINS
CVSS S Ground. Dedicated ground for the core CPU
CVDD S +VDD. Dedicated power supply for the core CPU
DVSS S Ground. Dedicated ground for I/O pins
DVDD S +VDD. Dedicated power supply for I/O pins
† I = Input, O = Output, Z = High-impedance, S = Supply
‡ These pins have Schmitt trigger inputs.
§ This pin has an internal bus holder controlled by way of the BSCR register.
¶ This pin has an internal pullup resistor.
# This pin has an internal pulldown resistor.
GPIO
MBus
64K RAM
Dual Access
Program/Data
McBSP1
McBSP2
McBSP3
RHEA Bus
APLL
TIMER
JTAG
Clocks
RHEAbus
RHEA
Bridge
TI BUS
xDMA
logic
16K Program
ROM
Pbus Cbus Dbus Ebus
RHEA
bus
MBus
64K RAM
Single Access
Program
Cbus Dbus
Ebus
Pbus Cbus Dbus
Ebus
Pbus
Enhanced XIO
P, C, D, E Buses and Control Signals
XIO
16HPI
54X cLEAD
16 HPI
TMS320VC5416 Functional Block Diagram