41
U501:W78LE51
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
40
34
35
36
37
38
30
31
32
33
26
27
28
29
21
22
23
24
25
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.5, A13
P2.6, A14
P2.7, A15
P2.0, A8
P2.1, A9
P2.2, A10
P2.3, A11
P2.4, A12
P1.0
P1.2
P1.3
P1.4
P1.5
P1.6
RXD, P3.0
TXD, P3.1
P1.7
RST
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL1
XTAL2
VSS
P1.1
SYMBOL
DESCRIPTIONS
EA
EXTERNAL ACCESS ENABLE
: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
data will not be presented on the bus if EA pin is high and the program counter is
within on-chip ROM area.
PSEN
PROGRAM STORE ENABLE
: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin.
ALE
ADDRESS LATCH ENABLE
: ALE is used to enable the address latch that separates
the address from the data on Port 0.
RST
RESET
: A high on this pin for two machine cycles while the oscillator is running resets
the device.
XTAL1
CRYSTAL1
: This is the crystal oscillator input. This pin may be driven by an external
clock.
XTAL2
CRYSTAL2
: This is the crystal oscillator output. It is the inversion of XTAL1.
V
SS
GROUND
: Ground potential
V
DD
POWER SUPPLY
: Supply voltage for operation.
P0.0
−
P0.7
PORT 0
: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The Port 0 is also an open-drain
port and external pull-ups need to be connected while in programming.
P1.0
−
P1.7
PORT 1
: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
P2.0
−
P2.7
PORT 2
: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0
−
P3.7
PORT 3
: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) :External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
P4.0
−
P4.3
PORT 4:
Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O port or external interrupt input sources
(INT2 /INT3 ).
Содержание DV4300
Страница 22: ...30 29 11 PARTS LOCATION FRONT FU1 FRONT RCU RCU Q701 Q702 Q703 Q602 Q601 Q603 Q604 Q803 Q802 Q801 Q806 Q804...
Страница 24: ...32 POWER SUPPLY SMPS PQ1 PQ14 PQ13 PQ9 PQ8 PQ5 PQ6 PQ4 PQ7 PQ3 PU6 PU3...
Страница 25: ...33 U201 ES6028 12 MICROPROCESSOR AND IC DATA...
Страница 26: ...34 U201 ES6028...
Страница 27: ...35 U201 ES6028...
Страница 28: ...36 U201 ES6028...
Страница 29: ...37 U201 ES6028...
Страница 30: ...38 U201 ES6028...
Страница 31: ...39 U201 ES6028...
Страница 38: ...46 13 WAVE FORM CHART 1 CE 2 WE 3 OE 4 DSCK 5 RAS0 6 CS 7 DDAC 8 CDAC...
Страница 39: ...47 9 BDAC 10 ADAC 11 CVBS 12 R Pr 13 C B Pb 14 Y G Yp 15 TSDO 16 BCLK...
Страница 40: ...48 17 LRCK 18 MCLK 19 FLO_RCA 20 FRO_RCA 21 ALO_TVS 22 ARO_TVS 23 MUTE 24 HOST_DATA...
Страница 41: ...49 25 HOST_CS 26 HOST_CLK 27 Y G Yp3 28 C B Pb3 29 R Pr3 30 VFD_DATA 31 VFD_CLK 32 VFD_CS...