43
IC21 : T5CD2
Pin
No.
Port Name
I/O Use Power
off
Name
Port Setting
Note
Act.
init
1 VREFH
VREFH
ADC power, connect with +5V
2 AVSS
GND
GND
3 AVCC
AVCC
MCU power, connect with +5V
4 P70/TA0IN
I/O
O
L
/SRAM_WE
L
I
sram write enable
5 P71/TA1OUT
I/O
O
L
/SRAM_OE
L
I
sram output enable
6 P72/TA3OUT
I/O
O
L
/SRAM_CE
L
I
sram chip enable
7 P73/TA4IN
I/O
NC
open
8 P74/TA5OUT
I/O
NC
open
9 P75/INT0
I/O
I
-
RS/REMOTE
-
I
remote in
10 P80/TB0IN0/INT5
I/O I/O
L
SRAM_DATA00
-
I
sram_data_00
11 P81/TB0IN1/INT6
I/O I/O
L
SRAM_DATA01
-
I
sram_data_01
12 P82/TB0OUT0
I/O I/O
L
SRAM_DATA02
-
I
sram_data_02
13 P83/TB0OUT1
I/O I/O
L
SRAM_DATA03
-
I
sram_data_03
14 P84/TB1IN0/INT7
I/O I/O
L
SRAM_DATA04
-
I
sram_data_04
15 P85/TB1IN1/INT8
I/O I/O
L
SRAM_DATA05
-
I
sram_data_05
16 P86/TB1OUT0
I/O I/O
L
SRAM_DATA06
-
I
sram_data_06
17 P87/TB1OUT1
I/O I/O
L
SRAM_DATA07
-
I
sram_data_07
18 P90/TXD0
I/O
O
L
VFD_DATA
-
vfd data
19 P91/RXD0
I/O
O
L
VFD_CS
L
vfd chip select
20 P92/SCLK0/CTS0
I/O
O
L
VFD_CLK
L
I
vfd clock
21 P93/TXD1
I/O
O
L
UPDATE_TXD
-
I
used when connect with update tool
22 P94/RXD1
I/O
I
I
UPDATE_RXD
-
I
used when connect with update tool
23 P95/SCLK1/CTS1
I/O
NC
-
I
open
24 AM0
AM0
chip operate select, connect with +5V
25 DVCC
DVCC
MCU power, connect with +5V
26 X2
X2
oscillator(20MHz)
27 DVSS
DVSS
GND
28 X1
X1
oscillator(20MHz)
29 AM1
AM1
chip operate select, connect with +5V
30 /RESET
/RESET
MCU reset
31 P96/XT1
I/O
NC
open
32 P97/XT2
I/O
NC
open
33 /BOOT/EMU0
BOOT
update mode select
34 EMU1
I/O
NC
open
35 PA0/TB2IN0/INT1
I/O
I
-
RS/REMOTE
-
I
remote in
36 PA1/TB2IN1/INT2
I/O
NC
open
37 PA2/TB2OUT0
I/O
O
H
BUSOUT
-
I
bus out
38 PA3/TB2OUT1
I/O
I
-
SYSTEM_DETECT
-
I
system detect
39 P40/CS0/SCOUT
I/O
O
-
RS_ON/OFF
-
I
remote signal kill control
40 P41/CS1/TXD2
I/O
O
L
CTRL
H
I
Unit power control
41 P42/CS2/RXD2
I/O
O
H
LED
L
stanby LED control
42 P43/CS3/SCLK2/CTS2
I/O
NC
open
43 P44/ALE
I/O
NC
open
44 P00/AD0
I/O
O
L
SRAM_ADD00
-
I
sram_address_00
45 P01/AD1
I/O
O
L
SRAM_ADD01
-
I
sram_address_01
46 P02/AD2
I/O
O
L
SRAM_ADD02
-
I
sram_address_02
47 P03/AD3
I/O
O
L
SRAM_ADD03
-
I
sram_address_03
48 P04/AD4
I/O
O
L
SRAM_ADD04
-
I
sram_address_04
49 P05/AD5
I/O
O
L
SRAM_ADD05
-
I
sram_address_05
50 P06/AD6
I/O
O
L
SRAM_ADD06
-
I
sram_address_06
Содержание CD5003/B
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