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BIOS
Choose Enabled or Disabled (default). In order to improve
performance, certain space in memory can be reserved for
ISA cards. This memory must be mapped into the memorys
space below 16MB. Enbable this option will cause memory
only connect to 16MB.
Memory Hole
DRAM optimization feature: If a memory read is addressed to
a location whose latest write is being held in a buffer before
being written to memory, the read is satisfied through the buffer
contents, and the read is not sent to the DRAM.
The choice:
Enabled,
Disabled
Read Around Write
You can select CAS latency time in HCLKs of 2/2 or 3/3. The
system board designer should have set the values in this field,
depending on the DRAM installed. Do not change the values
in this field unless you change specifications of the installed
DRAM or the installed CPU.
SDRAM Cycle Length
The setting of this item must depend on the spec of PC100/
PC133. For example, if user chooses HCLK + 33M, that
means not only the motherboard but also the SDRAM needs
to comply with PC-133 spec.
Choice: Host CLK(default), HCLK-33M or HCLK+33M.
DRAM CLOCK
When disabled, CPU bus will be occupied during the entire
PCI operation period.
The choice:
Enabled,
Disabled
Concurrent PCI / Host
This item allows you to select the value in this field, depend-
ing on whether the board has paged DRAMs or EDO
(extended data output) DRAMs.
The choice:
EDO 50ns,
EDO 60ns,
Slow,
Medium,
Fast,
Turbo
Bank 0/1 2/3 4/5 DRAM
Timing
Choose Enabled or Disabled (default). When Enabled, the
access to the system BIOS ROM addressed at F0000H-
FFFFFH is cached.
System BIOS
Cacheable
