K7VAT
System Board 58
Values
Meaning
Enabled
A PCI Master can request a pipeline.
PCI Master
Pipeline Req.
Disabled
No pipeline is granted to any Master.
Enabled
The CPU Host is free for other transactions while a PCI
transaction takes place.
P2C / C2P
concurrency
Disabled
The CPU Host bus is always forced to wait while a PCI
transaction takes place.
Enabled
If a memory read is addressed to a location whose latest write
is being held in a buffer before being written to memory, the
read is satisfied through the buffer contents, and the read is
not sent to the DRAM.
Fast R-W turn
around
Disabled
This feature is disabled.
Enabled
When enabled CPU writes to PCI are buffered, the CPU will
not have to wait for the transaction to finish.
CPU to PCI
write buffer
Disabled
The CPU will have to wait for each PCI write to finish before
a new write can be initiated.
Enabled
All transactions are buffered, and transactions that are
burstable (successive) will be conducted in a PCI burst
transaction.
PCI dynamic
bursting
Disabled
PCI burst transactions are disabled.
Enabled
PCI Master 0
WS write
Disabled
Enabled
The chipset has a write buffer that supports delayed
transactions. Enable this item for PCI 2.1 compliance.
PCI delay
transaction
Disabled
This will shut down use of the integrated buffer, no delayed
transactions are allowed.
Enabled
When #2 (AGP port) tries to access #1 (PCI) and an error
occurs, the transaction will be tried again.
PCI #2 Access
#1 retry
Disabled
No retry will occur.
