VIA694X System Board 40
DRAM Clock
:Host CLK
(default)
System shows the actual DRAM speed the system uses.
:HCLK-33M
:HCLK+33M
Please check DRAM clock for optimizes selection.
Memory Hole :
this field enable a memory hole in main memory space. CPU
cycles matching an enabled hold are passed on to PCI note that a selected can not
be changed while the L2 cache is enabled.
:Disabled
(default)
:15M-16M
P2C/C2P Concurrency
:Enabled
(default)
:Disabled
Fast R-W Turn Around
:Enabled
:Disabled
(default)
System BIOS Cacheable
:Enabled
(default)
:Disabled
Video RAM Cacheable
:Enabled
(default)
--- allows caching of the video RAM, resulting in better system
performance. However, if any program writes to this memory area, a system error
may occur.
:Disabled
AGP Aperture Size
To select the size of the Accelerated Graphics Port (AGP) aperture is a portion of
the PCI memory address range dedicated for graphics memory address space.
Host cycles that hit the aperture range are forwarded to the AGP without any
translation.