INTEL 810
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SDRAM RAS to CAS delay
This controls the DRAM page miss and row miss leadoff timing.
: 2
: 3 (default)
SDRAM RAS Precharge Time
SDRAM precharge time by RAS.
: 2
: 3 (default)
System BIOS cacheable
define whether system BIOS area cacheable or not.
:Enabled (default)
:Disabled
Video BIOS cacheable: to define whether video BIOS area cacheable or not.
:Enabled (default)
:Disabled
Memory Hole at 15M-16M: this field enable a memory hole in main memory
space. CPU cycles matching an enabled hold are passed on to PCI note that a
selected can not be changed while the L2 cache is enabled.
:Enabled
:Disabled (default)
Delay Transaction
:Enabled
:Disabled(default)
Onboard Display Cache Setting
CAS# Latency
:3(default)
:2
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