Lucent Technologies DSP1611, Информационное руководство

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
JTAG Test Access Port April 1998
11-10
DRAFT COPY
Lucent Technologies Inc.
11.3 Elements of the JTAG Test Logic
(continued)
11.3.4 The Boundary-Scan Register—JBSR (continued)
Table 11-4. JTAG Scan Register (DSP1627/28/29 Only)
Note: The direction of shifting is from TDI to cell 104, to cell 103, . . . , to cell 0, and to TDO.
Cell Type Signal Name/Function Cell Type Signal Name/Function
0 OE Controls cells 1, 27—31 69 B OCK2/PCSN
†
1 O CKO 70 DC Controls cell 71
2 I RSTB 71 B DO2/PSTAT
†
3 DC Controls cell 4 72 DC Controls cell 73
4 B TRAP 73 B SYNC2/PDSEL
†
5 I STOP
‡
74 DC Controls cell 75
6 O IACK 75 B ILD2/PIDS
†
7 I INT0 76 DC Controls cell 77
8 OE Controls cells 6, 10—25, 49, 50, 78, 79 77 B OLD2/PODS
†
9 I INT1 78 O IBF2/PIBF
†
10—25 O AB[15:0] 79 O OBE2/POBE
†
26 I EXM 80 DC Controls cell 81
27 O RWN 81 B ICK2/PB0
†
28—31 O EROM, ERAMLO, ERAMHI, IO 82 DC Controls cell 83
32—36 B DB[4:0] 83 B DI2/PB1
†
37 DC Controls cells 32—36, 38—48 84 DC Controls cell 85
38—48 B DB[15:5] 85 B DOEN2/PB2
†
49 O OBE1 86 DC Controls cell 87
50 O IBF1 87 B SADD2/PB3
†
51 I DI1 88 DC Controls cell 89
52 DC Controls cell 53 89 B IOBIT0/PB4
†
53 B ILD1 90 DC Controls cell 91
54 DC Controls cell 55 91 B IOBIT1/PB5
†
55 B ICK1 92 DC Controls cell 93
56 DC Controls cell 57 93 B IOBIT2/PB6
†
57 B OCK1 94 DC Controls cell 95
58 DC Controls cell 59 95 B IOBIT3/PB7
†
59 B OLD1 96 DC Controls cell 97
60 OE Controls cell 61 97 B VEC3/IOBIT4
†
61 O DO1 98 DC Controls cell 99
62 DC Controls cell 63 99 B VEC2/IOBIT5
†
63 B SYNC1 100 DC Controls cell 101
64 DC Controls cell 65 101 B VEC1/IOBIT6
†
65 B SADD1 102 DC Controls cell 103
66 DC Controls cell 67 103 B VEC0/IOBIT7
†
67 B DOEN1 104 I
Clock Generator
§
68 DC Controls cell 69
† Please refer to pin multiplexing in Section 9.4, PHIF Pin Multiplexing , Section 10.1.4, BIO Pin Multiplexing , and Section 7.7.1, SIO2 Features ,
for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2.
‡ Shifting a zero into this cell in the mode to scan a zero into the device will disable the processor clocks the same as the STOP pin will.
§ Indicates signal is internal and not necessarily observable at pins depending on how the JTAG is set up. If the JTAG SAMPLE instruction is
used, this cell will have a logic one regardless of the state of the pin.