LSI Logic Confidential
WRREQ = 0
9-3
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
9.1
WRREQ = 0
When WRREQ = 0, the SBP may be a bitstream output (BRSD = 1) or
input (BRSD = 0) as described in the following two sections.
9.1.1
Bitstream Output – Outgoing Transfers (BRSD = 1)
When the SBP is a bitstream output for WRREQ = 0:
•
SBP_REQ is asserted along with the oldest byte of bitstream data
on each clock in which the bitstream FIFO is not empty (partially
filled or full).
•
SBP_RD is asserted as long as the DMA transfer is enabled (Go is
set in the Secondary Bitstream Configuration register and the
Secondary Next Address is not equal to the Secondary Stop
Address) to indicate the direction of the transfer.
When the system asserts SBP_ACK in a clock in which SBP_REQ is
asserted, the oldest byte of bitstream data is removed from the FIFO at
the end of the clock, and the next oldest byte (if present) in the FIFO is
presented on the next clock.
shows outgoing transfers from the bitstream port with
WRREQ = 0, POL = 1 and BSRD = 1. In the figure, note that SBP_ACK
and SBP_REQ are shown as active LOW. The DMN-8600 processor
drives SBP_DATA.
Figure 9.2
Bitstream Port Outgoing Transfers with WRREQ = 0,
POL = 1 and BSRD = 1
SBP_CLK (I)
SBP_REQ (O)
SBP_RD (O)
SBP_ACK (I)
SBP_DATA (O)
Data
Data
Data
Содержание DMN-8600
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