LSI Logic Confidential
8-22
Host Slave Interface
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
8.7
Host DMA Registers
All host DMA registers are 32-bit CBus registers which are accessible to
the SPARC core or Host Interface using 32-bit loads or stores.
8.7.1
Host DMA Configuration Register (CBus Address: 0x60060)
This register at control bus address 0x60060 specifies Host DMA
configuration information.
Host DMA Configuration Register
CBus Address: 0x60060
IE
4
If IE is set, then a Host DMA completion interrupt is
generated when a host DMA transfer completes;
otherwise no interrupt is generated.
If IE is clear, no Host completion interrupt is generated.
Incoming transfers are complete when the value of the
Host DMA Next Address register equals the value of the
Host DMA Stop Address register, and the DMA data has
been written to SDRAM.
Outgoing transfers are complete when the value of Host
DMA Next Address equals the value of the Host DMA
Stop Address, and the DMA data has been transferred to
the system. In other words, the DMA FIFO is empty.
1 = Host completion interrupt enabled
0 = Host completion interrupt disabled
GO
3
GO is set by microcode or by the host processor to begin
host DMA transfers.
31
16
Reserved
15
5
4
3
2
1
0
Reserved
IE
GO
POL BSRD WRData
Содержание DMN-8600
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