LSI Logic Confidential
18-30
Specifications
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
•
For legend for S, R, F, and M{a,b}, see Notes following
18.2.7 Audio Timing
Audio AC timing is shown in
and is referenced in
.
Figure 18.24 Audio Input/Output AC Timing
Note:
Diagram shown is with falling driving edge/rising sampling
edge. The same parameters are valid for rising driving
edge/falling sample edge.
.
T
1
Driving Edge
AI_MCLKO (O)
AO_MCLKO (O)
AI_SCLK (I/O)
AO_SCLK (O)
FSYNC, Data (O)
FSYNC, Data (I)
Sampling Edge
70%
50%
30%
T
CYC
T
HIGH
T
LOW
T
4
T
2
T
3
Table 18.19 Audio Input/Output AC Timing Parameters
Symbol
Description
Min
1
Typ
Max
Unit
T
CYC
MCLK cycle clock period
19.2
ns
T
HIGH
MCLK high pulse width
8.5
T
LOW
MCLK low pulse width
8.5
Содержание DMN-8600
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