Application Note 124
AN124-2
an124f
Numerous details contribute to the circuit’s performance.
The 1300μF capacitor, a highly specialized type, is selected
for leakage in accordance with the procedure given in
Appendix B. Further, it, and its associated low noise 1.2k
resistor, are fully shielded against pick-up. FETs Q1 and
Q2 differentially feed A2, forming a simple low noise op
amp. Feedback, provided by the 100k - 10Ω pair, sets
closed loop gain at 10,000. Although Q1 and Q2 have
extraordinarily low noise characteristics, their offset and
drift are uncontrolled. A1 corrects these defi ciencies by
adjusting Q1’s channel current via Q3 to minimize the
Q1-Q2 input difference. Q1’s skewed drain values ensure
that A1 is able to capture the offset. A1 and Q3 supply
whatever current is required into Q1’s channel to force
offset within about 30μV. The FETs’ V
GS
can vary over
a 4:1 range. Because of this, they must be selected for
10% V
GS
matching. This matching allows A1 to capture
the offset without introducing signifi cant noise. Q1 and
Q2 are thermally mated and lagged in epoxy at a time
constant much greater than A1’s DC stabilizing loop roll-
off, preventing offset instability and hunting. The entire
A1-Q1-Q2-A2 assembly and the reference under test are
completely enclosed within a shielded can.
1
The reference
is powered by a 9V battery to minimize noise and insure
freedom from ground loops.
Peak-to-peak detector design considerations include J-FET’s
used as peak trapping diodes to obtain lower leakage than
afforded by conventional diodes. Diodes at the FET gates
clamp reverse voltage, further minimizing leakage.
2
The peak
storage capacitors highly asymmetric charge-discharge
profi le necessitates the low dielectric absorption polypro-
pelene capacitors specifi ed.
3
Oscilloscope connections via
galvanically isolated links prevent ground loop induced
corruption. The oscilloscope input signal is supplied by an
isolated probe; the sweep gate output is interfaced with an
isolation pulse transformer. Details appear in Appendix C.
Noise Measurement Circuit Performance
Circuit performance must be characterized prior to mea-
suring LTC6655 noise. The pre-amplifi er stage is verifi ed
for >10Hz bandwidth by applying a 1μV step at its input
(reference disconnected) and monitoring A2’s output.
Figure 4’s 10ms risetime indicates 35Hz response, insuring
the entire 0.1Hz to 10Hz noise spectrum is supplied to the
succeeding fi lter stage.
Note 1.
The pre-amplifi er structure must be carefully prepared. See
Appendix A, “Mechanical and Layout Considerations”, for detail on pre-
amplifi er construction.
Note 2.
Diode connected J-FET’s superior leakage derives from their
extremely small area gate-channel junction. In general, J-FET’s leak a few
picoamperes (25°C) while common signal diodes (e.g. 1N4148) are about
1,000X worse (units of nanoamperes at 25°C).
Note 3.
Tefl on and polystyrene dielectrics are even better but the Real
World intrudes. Tefl on is expensive and excessively large at 1μF. Analog
types mourn the imminent passing of the polystyrene era as the sole
manufacturer of polystyrene fi lm has ceased production.
AN124 F02
SWEEP
GATE OUT
DC OUT
0V TO 1V = 0μV
P-P
TO
1μV
P-P
AT INPUT
VERTICAL
INPUT
≈700nV
NOISE
0.1Hz TO 10Hz
OSCILLOSCOPE
OUTPUT
A = 10
6
0.1Hz TO 10Hz FILTER AND
PEAK TO PEAK NOISE DETECTOR
0μV TO 1μV = 0V TO 1V, A = 100
LOW NOISE
AC PRE-AMP
E
N
, 0.1Hz TO 10Hz = 160nV
A = 10,000
RESET
LTC6655
2.5V REFERENCE
Figure 2. Conceptual 0.1Hz to 10Hz Noise Testing Scheme Includes Low Noise Pre-Amplifi er, Filter and Peak to Peak Noise
Detector. Pre-Amplifi er’s 160nV Noise Floor, Enabling Accurate Measurement, Requires Special Design and Layout Techniques
