DC861 QUICK START GUIDE
2
Note 1:
States 13, 14 and 15 (binary 11xx) are not used. Programming a channel to states 8 or higher w ill configure that particular channel
into a low pow er shutdow n state. In addition, programming a channel into state 15 (binary 1111) w ill cause that particular channel to draw
up to 20mA of supply current and is not recommended.
(Note 1)
(
Note 1)
D escription of the 3-W ire SPI Interface
G ain control of each amplifier is independently programmable
using the 3-wire SPI interface (see Figure 3). Logic levels for
the LTC6912 3-wire serial interface are TTL/CM O S compatible.
W hen CS/LD is low, the serial data on DIN is shifted into an 8-
bit shift-register on the rising edge of the clock, with the M SB
transferred first. Serial data on DO UT is shifted out on the
clock’s falling edge. A rising edge on CS/LD will latch the shift-
register’s contents into an 8-bit D-latch and disable the clock
internally on the IC. The upper nibble of the D-latch (4 most
significant bits), configures the gain for the B-channel ampli-
fier. The lower nibble of the D-latch (4 least significant bits),
configures the gain for the A-channel amplifier. Tables 1 and 2
detail the nominal gains and respective gain codes.
Figure 3.Block Diagram, LTC6912-1/2 Serial Interface