2
dc2077af
DEMO MANUAL DC2077A
PERFORMANCE SUMMARY
OPERATION
Table 1. Typical Demo Board Performance Summary
SYMBOL
PARAMETER
CONDITIONS
VALUE / UNIT
Power Supply
V
CC
Operating Supply Range
All V
CC
Pins Plus OUT
4.75V to 5.25V
I
CC
Current Consumption
Total Current
95mA
T
A
= 25°C, V
CC
= 5V
FREQUENCY
(MHZ)
POWER GAIN
|S21|
OUTPUT
THIRD-ORDER
INTERCEPT
POINT
1
OIP3
OUTPUT
THIRD-ORDER
INTERMODU-
LATION
1
OIM3
SECOND
HARMONIC
DISTORTION
2
HD2
THIRD HARMONIC
DISTORTION
2
HD3
OUTPUT 1DB
COMPRESSION
POINT
P1DB
NOISE FIGURE
3
NF
100
20.2
47.2
–90.4
–56.8
–96.7
23.2
3.2
200
20.6
48.0
–91.9
–55.6
–92.9
22.4
2.7
240
20.6
47.9
–91.9
–52.5
–106.1
22.0
2.7
300
20.7
47.9
–91.9
–50.5
–83.1
21.8
2.8
400
20.6
46.9
–89.9
–50.4
–77.4
21.7
2.8
500
20.6
45.0
–86.0
–47.8
–72.6
21.8
2.9
600
20.6
42.5
–81.0
–43.7
–64.0
21.7
3.1
700
20.5
39.7
–75.5
–42.1
–60.7
21.4
3.3
800
20.5
38.6
–73.1
–40.6
–63.1
21.4
3.4
900
20.5
37.1
–70.3
–37.1
–60.4
21.1
3.7
1000
20.4
36.0
–68.0
–36.9
–55.1
20.8
3.8
1100
20.3
35.1
–66.2
–35.7
–54.5
20.4
3.9
1200
20.2
34.4
–64.8
–34.4
–53.6
20.3
4.1
Units
dB
dBm
dBc
dBc
dBc
dBm
dB
Notes: All figures are referenced to J1 (Input Port) and J2 (Output Port).
1. Two-tone test conditions: Output power level = +2dBm/tone, tone spacing = 1MHz.
2. Single-tone test conditions: Output power level = +6dBm.
3. Small-signal noise figure.
The demo circuit 2077A is a high linearity, fixed gain
amplifier. It is designed for ease of use. Both the input
and output are internally matched to 50Ω single-ended
source and load impedance. Figure 2 shows the DC2077A’s
S-parameters.
Figure 4 shows the demo circuit’s schematic. The input and
output DC blocking capacitors (C1 and C7) are required
because this device is internally DC biased for optimal
operation. The frequency appropriate choke (L1) and the
decoupling capacitors (C3 and C4) provide the proper
DC bias to the RF output node. Only a single 5V supply is
necessary for the VCC pins on the device.
L2 and C6 are optional parts. These additional components
allow for further optimization to lower or wider frequency
range applications.
A parallel 62pF (C2) and 348Ω (R1) input network has
been added to ensure low frequency stability. Note that the
input stability network does degrade performance below
150MHz. Low frequency performance can be improved
by increasing the value of capacitor C2.
The T_DIODE Pin (Turret E1) can be forward biased to
ground with 1mA of current. The measured voltage will
be an indicator of the chip junction temperature (T
J
).
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