Linear Technology LTC2391-16, Демонстрационное руководство

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dc1501A
DEMO MANUAL DC1501A
Data Collection
This demo board is tested in house by duplicating the FFT plot
shown in the ADC data sheet. This involves using a low jitter,
1MHz (500kHz for LTC2392-16, 250kHz for LTC2391-16)
clock source for the encode clock, along with a low noise,
low distortion sinusoidal generator at a frequency of 20kHz.
The input signal level is approximately –1dBfs.
The input is fi ltered with a 20kHz single pole RC fi lter
shown in Figure 5. The FFT shown in the data sheet is a
16384-point FFT. A typical FFT obtained with DC1501A
is shown in Figure 6. Note that to get the real SNR, the
DC1501A SETUP
Figure 3. AC-Coupled Differential Driver
Figure 4. DC Coupled Differential Driver
signal level (–1dB) has to be added back to the SNR that
PScope displays. With the example shown in Figure 6 this
means that the actual SNR would be 94.061dB. Taking the
RMS sum of the recalculated SNR and the THD yields a
SINAD of 93.75dB which is fairly close to the typical value
for this ADC.
There are a number of scenarios that can produce
misleading results when evaluating an ADC. One that is
common is feeding the converter with a frequency, that
is a sub-multiple of the sample rate, and which will only
exercise a small subset of the possible output codes.