manualshive.com logo in svg

Linear Technology LTC2173-12, Руководство пользователя, Страница: 25 / 34

Поделиться
Скачать
Linear Technology LTC2173-12 Скачать руководство пользователя страница 25

25

21754312fa

LTC2175-12/

LTC2174-12/LTC2173-12

applicaTions inForMaTion

In nap mode any combination of A/D channels can be 

powered down while the internal reference circuits and the 

PLL stay active, allowing faster wakeup than from sleep 

mode. Recovering from nap mode requires at least 100 

clock cycles. If the application demands very accurate DC 

settling then an additional 50µs should be allowed so the 

on-chip references can settle from the slight temperature 

shift caused by the change in supply current as the A/D 

leaves nap mode. Nap mode is enabled by mode control 

register A1 in the serial programming mode.

DEVICE PROGRAMMING MODES
The operating modes of the LTC2175-12/LTC2174-12/

LTC2173-12 can be programmed by either a parallel in-

terface or a simple serial interface. The serial interface has 

more flexibility and can program all available modes. The 

parallel interface is more limited and can only program 

some of the more commonly used modes. 

Parallel Programming Mode
To use the parallel programming mode, PAR/

SER

 should 

be tied to V

DD

. The 

CS

, SCK, SDI and SDO pins are binary 

logic inputs that set certain operating modes. These pins 

can be tied to V

DD

 or ground, or driven by 1.8V, 2.5V, or 

3.3V CMOS logic. When used as an input, SDO should 

be driven through a 1k series resistor. Table 3 shows the 

modes set by 

CS

, SCK, SDI and SDO.

Serial Programming Mode
To use the serial programming mode, PAR/

SER

 should be 

tied to ground. The 

CS

, SCK, SDI and SDO pins become a 

serial interface that program the A/D mode control registers. 

Data is written to a register with a 16-bit serial word. Data 

can also be read back from a register to verify its contents.
Serial data transfer starts when 

CS

 is taken low. The data 

on the SDI pin is latched at the first 16 rising edges of 

SCK. Any SCK rising edges after the first 16 are ignored. 

The data transfer ends when 

CS

 is taken high again.

The first bit of the 16-bit input word is the R/

W

 bit. The 

next seven bits are the address of the register (A6:A0). 

The final eight bits are the register data (D7:D0).
If the R/

W

 bit is low, the serial data (D7:D0) will be writ-

ten to the register set by the address bits (A6:A0). If the 

R/

W

 bit is high, data in the register set by the address bits 

(A6:A0) will be read back on the SDO pin (see the Timing 

Diagrams sections). During a read back command the 

register is not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground 

with a 200Ω impedance. If register data is read back 

through SDO, an external 2k pull-up resistor is required. 

If serial data is only written and read back is not needed, 

then SDO can be left floating and no pull-up resistor is 

needed. Table 4 shows a map of the mode control registers.

Table 3. Parallel Programming Mode Control Bits (PAR/

SER

 = V

DD

)

Pin

DESCRIPTION

CS

2-Lane / 1-Lane Selection Bit
0 = 2-Lane, 16-Bit Serialization Output Mode
1 = 1-Lane, 14-Bit Serialization Output Mode

SCK

LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode

SDI

Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode

SDO

Internal Termination Selection Bit
0 = Internal Termination Disabled
1 = Internal Termination Enabled

Содержание LTC2173-12

Страница 1: ...ave PECL LVDS TTL or CMOS inputs An internal clock duty cycle stabilizer al lows high performance at full speed for a wide range of clock duty cycles n 4 Channel Simultaneous Sampling ADC n 70 6dB SNR...

Страница 2: ...ting for information on non standard lead based finish parts For more information on lead free part marking go to http www linear com leadfree For more information on tape and reel specifications go t...

Страница 3: ...2 FS Offset Matching 3 3 3 mV Transition Noise External Reference 0 3 0 3 0 3 LSBRMS Analog Input The l denotes the specifications which apply over the full operating temperature range otherwise speci...

Страница 4: ...put 140MHz Input l 84 90 90 90 84 90 90 90 85 90 90 90 dBFS dBFS dBFS S N D Signal to Noise Plus Distortion Ratio 5MHz Input 70MHz Input 140MHz Input l 68 6 70 6 70 4 70 68 7 70 6 70 4 70 68 9 70 6 70...

Страница 5: ...V RIN Input Resistance See Figure 11 30 k CIN Input Capacitance 3 5 pF DIGITAL INPUTS CS SDI SCK in Serial or Parallel Programming Mode SDO in Parallel Programming Mode VIH High Level Input Voltage V...

Страница 6: ...at TA 25 C Note 5 SYMBOL PARAMETER CONDITIONS LTC2175 12 LTC2174 12 LTC2173 12 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX fS Sampling Frequency Notes 10 11 l 5 125 5 105 5 80 MHz tENCL ENC Low Time No...

Страница 7: ...mped by internal diodes This product can handle input currents of greater than 100mA below GND without latchup Note 5 VDD OVDD 1 8V fSAMPLE 125MHz LTC2175 105MHz LTC2174 or 80MHz LTC2173 2 lane output...

Страница 8: ...SOFTWARE COMPATIBILITY WITH THE 14 BIT VERSIONS OF THESE A Ds DURING NORMAL NON OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0 SEE THE DATA FORMAT SECTION FOR MORE DETAILS Timing Diagrams 2 Lane O...

Страница 9: ...FR FR D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6 OUT B OUT B ANALOG INPUT ENC ENC DCO DCO tAP tENCH tENCL tSER tPD tDATA tFRAME SAMPLE N 6 SAMPLE N 5 SAMPLE N 4 N 1 N tSER tSER 217512 TD05 DX DY DX DY 0...

Страница 10: ...ING NORMAL NON OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0 SEE THE DATA FORMAT SECTION FOR MORE DETAILS One Lane Output Mode 12 Bit Serialization ANALOG INPUT ENC ENC DCO DCO tAP tENCH tENCL tSE...

Страница 11: ...sps LTC2175 12 8k Point FFT fIN 140MHz 1dBFS 125Msps LTC2175 12 8k Point 2 Tone FFT fIN 70MHz 75MHz 1dBFS 125Msps LTC2175 12 Shorted Input Histogram FREQUENCY MHz 0 100 110 120 70 60 80 90 AMPLITUDE d...

Страница 12: ...ity DNL LTC2174 12 8k Point FFT fIN 5MHz 1dBFS 105Msps SENSE PIN V 0 6 71 68 69 70 67 66 72 SNR dBFS 0 7 0 8 0 9 1 1 1 2 1 3 1 217512 G15 OUTPUT CODE 0 1 0 0 4 0 6 0 8 INL ERROR LSB 0 2 0 0 2 0 4 0 6...

Страница 13: ...50 300 350 217512 G23a LTC2174 12 SNR vs Input Frequency 1dB 2V Range 105Msps LTC2174 12 SFDR vs Input Frequency 1dB 2V Range 105Msps LTC2174 12 8k Point FFT fIN 70MHz 1dBFS 105Msps LTC2174 12 8k Poin...

Страница 14: ...DE 0 1 0 0 4 0 2 0 6 0 8 DNL ERROR LSB 0 0 4 0 2 0 6 0 8 1 0 1024 2048 3072 4096 217512 G42 FREQUENCY MHz 0 100 110 120 70 60 80 90 AMPLITUDE dBFS 50 30 40 20 10 0 10 20 30 40 217512 G43 FREQUENCY MHz...

Страница 15: ...S 80 60 50 40 30 20 10 0 80 70 SFDR dBc AND dBFS 90 100 110 70 60 50 40 30 20 10 0 217512 G52 dBFS dBc INPUT FREQUENCY MHz 0 90 85 80 75 70 65 95 SFDR dBFS 50 100 150 200 250 300 350 217512 G35a LTC21...

Страница 16: ...amming mode PAR SER 0V SCK is the serial interface clock input In the parallel programmingmode PAR SER VDD SCKselects3 5mA or 1 75mA LVDS output currents SCK can be driven with 1 8V to 3 3V logic SDI...

Страница 17: ...t current level is programmable There is an optional internal 100 termination resistor between the pins of each LVDS output pair OUT4B OUT4B OUT4A OUT4A Pins 23 24 Pins 25 26 Serial data outputs for C...

Страница 18: ...S H SENSE VREF 1 F 0 1 F 12 BIT ADC CORE 12 BIT ADC CORE 12 BIT ADC CORE 12 BIT ADC CORE OVDD 1 8V ENC ENC PLL OUT1A OUT1A OUT1B OUT1B OUT2A OUT2A OUT2B OUT2B DATA CLOCK OUT DATA CLOCK OUT OUT3A OUT3...

Страница 19: ...d swing from VCM 0 5V to VCM 0 5V There should be 180 phase difference between the inputs Thefourchannelsaresimultaneouslysampledbyashared encode circuit Figure 2 INPUT DRIVE CIRCUITS Input Filtering...

Страница 20: ...A 007159 000000 T2 COILCRAFT WBC1 1LB RESISTORS CAPACITORS ARE 0402 PACKAGE SIZE 217512 F05 LTC2175 12 25 25 50 0 1 F 2 7nH 2 7nH AIN AIN 0 1 F VCM ANALOG INPUT 0 1 F 0 1 F T1 T1 MA COM ETC1 1 13 RESI...

Страница 21: ...ackside of the circuit board Encode Input The signal quality of the encode inputs strongly affects the A D noise performance The encode inputs should be treated as analog signals do not route them nex...

Страница 22: ...3 6V so 1 8V to3 3VCMOSlogiclevelscanbeused TheENC threshold is 0 9V For good jitter performance ENC should have fast rise and fall times Clock PLL and Duty Cycle Stabilizer Theencodeclockismultiplie...

Страница 23: ...urrent The default output driver current is 3 5mA This current can be adjusted by control register A2 in the serial pro gramming mode Available current levels are 1 75mA 2 1mA 2 5mA 3mA 3 5mA 4mA and...

Страница 24: ...randomized by applying an exclusive OR logic operation between the LSB and all other data output bits To decode the reverse operation is applied an exclusive OR operation is applied between the LSB a...

Страница 25: ...a serialinterfacethatprogramtheA Dmodecontrolregisters Data is written to a register with a 16 bit serial word Data can also be read back from a register to verify its contents Serial data transfer st...

Страница 26: ...zero GROUNDING AND BYPASSING The LTC2175 12 LTC2174 12 LTC2173 12 requires a printed circuit board with a clean unbroken ground plane A multilayer board with an internal ground plane in the first lay...

Страница 27: ...nal termination should only be used with 1 75mA 2 1mA or 2 5mA LVDS output current modes Bit 3 OUTOFF Output Disable Bit 0 Digital Outputs are Enabled 1 Digital Outputs are Disabled Bits 2 0 OUTMODE2...

Страница 28: ...LTC2175 12 LTC2174 12 LTC2173 12 28 21754312fa Typical Applications Silkscreen Top Top Side...

Страница 29: ...29 21754312fa LTC2175 12 LTC2174 12 LTC2173 12 TYPICAL Applications Inner Layer 2 GND Inner Layer 3 Inner Layer 4 Inner Layer 5 Power...

Страница 30: ...LTC2175 12 LTC2174 12 LTC2173 12 30 21754312fa TYPICAL Applications Bottom Side Silkscreen Bottom...

Страница 31: ...NC ENC CS SCK SDI GND OUT4B OUT4B OUT4A OUT4A 16 15 VDD 17 18 19 20 21 22 23 24 25 26 V DD V DD SENSE GND V REF PAR SER SDO GND OUT1A OUT1A OUT1B OUT1B 51 52 50 49 48 SDO PAR SER SENSE VDD 47 46 45 44...

Страница 32: ...ATED 6 SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK SEE NOTE 6 PIN 1 NOTCH R 0 30 TYP OR 0 35 45 C CHAMFER 0 40 0 10 52 51 1 2 BOTTOM VIEW EXPOSED...

Страница 33: ...echnology Corporation makes no representa tion that the interconnection of its circuits as described herein will not infringe on existing patent rights Revision History REV DATE DESCRIPTION PAGE NUMBE...

Страница 34: ...268 14 14 Bit 80Msps 105Msps 125Msps 1 8V Dual ADCs Ultralow Power 216mW 250mW 293mW 73 4dB SNR 85dB SFDR Serial LVDS Outputs 6mm 6mm QFN 36 LTC2266 12 LTC2267 12 LTC2268 12 12 Bit 80Msps 105Msps 125M...

Отзывы:

Нет отзывов