7
DEMO MANUAL DC236
DESIGN-READY SWITCHERS
Burst Mode operation allows the output MOSFETs to
“sleep” between several PWM switching cycle periods of
normal MOSFET activity. The current loss due to charging
the MOSFETs is not present during these “sleeping”
periods. Hysteretic output voltage detection results in a
slight increase of output voltage ripple during Burst Mode
operation. Bursting starts at approximately 20% of maxi-
mum designed load current.
The burst disable mode allows heavily discontinuous,
constant-frequency operation down to approximately 1%
of maximum designed load current. This mode results in
the elimination of switching frequency subharmonics over
99% of the output load range. Switching cycles start to be
dropped at approximately 1% of maximum designed load
current in order to maintain proper output voltage.
The FCB input pin allows the selection of the low current
operating mode of both switching regulator controllers.
Burst disable mode is enabled when the FCB pin is tied to
INTV
CC
.
Tying the FCB pin to ground potential forces the controller
into PWM or forced continuous mode. In forced continu-
ous mode, the output MOSFETs are always driven, regard-
less of output loading conditions. Operating in this mode
allows the switching regulator to source or sink current—
but be careful: when the output stage sinks current, power
is transferred back into the input supply terminals and the
input voltage rises.
Burst Mode operation is enabled when the voltage applied
to the FCB pin is less than (INTV
CC
– 0.8V) or if the pin is
left open. A comparator, having a precision 0.8V thresh-
old, allows the pin to be used to regulate a secondary
winding on the switching regulator’s output. A small
amount of hysteresis is included in the design of the
comparator to facilitate clean secondary operation. When
the resistively divided secondary output voltage falls
below the 0.8V threshold, the controller operates in the
forced continuous operating mode for as long as it takes
to bring the secondary voltage above the 0.8V + hysteresis
level.
The FLTCPL pin allows coupling between the two con-
trollers in several situations. The controllers will act
independently when FLTCPL is grounded. When the pin
is tied to INTV
CC
the following operations result:
1. When the FCB input voltage falls below its 0.8V thresh-
old, both controllers go into a forced continuous oper-
ating mode.
2. When either controller latches off due to an overload
condition (or short circuit), the other channel will be
latched off as well. Either the STBYMD mode pin or both
RUN/SS1 and RUN/SS2 pins need to be pulled to
ground in order to unlatch this condition. The STBYMD
mode pin internally pulls down both RUN/SS pins when
grounded. If the latches are defeated through the use of
an external pull-up current, neither latch will be acti-
vated.
The STBYMD PC board input is tied to the STBYMD IC pin.
Pulling the STBYMD IC pin up with greater than 5
µ
A to
the input supply turns on the internal 5V INTV
CC
and the
3.3V LDO regulators when neither of the two switching
regulator controllers is turned on. The 5V INTV
CC
regula-
tor will supply up to 50mA
RMS
and the 3.3V LDO will
supply up to 25mA
RMS
. Peak currents may be significantly
higher but internal power dissipation must be calculated to
guarantee that die temperature does not exceed the data
sheet specifications.
The demonstration board is shipped in a standard configu-
ration of 5V/3.3V but may be modified to produce output
voltages as low as 0.8V. Modifications will require changes
to the resistive voltage feedback divider and, in some
cases, the I
TH
pin compensation components.
Efficiency measurement depends on the operating condi-
tions of both regulators and must be performed thought-
fully and carefully. The maximum efficiency will occur with
the minimum required circuitry operating on an individual
regulator. Since there is much common circuitry operat-
ing in the IC when both regulators are running, overall
efficiency numbers will actually increase when the two
switching regulators are active. The increase is not signifi-
cant at high output currents but can become very signifi-
cant at low output currents, when the IC supply current
becomes an appreciable part of the total input supply
current.
OPERATIO
U
