LTC4125
24
4125f
For more information
BOARD LAYOUT CONSIDERATIONS
When using an LTC4125 circuit, care must be taken when
handling the board since high voltage is generated in
the resonant LC tank. Figure 18 indicates in red the high
voltage nodes that are present in a typical circuit. With
careful layout the area of these high voltage nodes should
be minimized and isolated for safe and simple operation.
For accurate sensing of the input current, the sense lines
from R
IS
must use proper Kelvin connections all the way
back to the sense resistor terminals as shown in Figure 18.
The lines connected to these resistors must be routed close
together (the loop area between the sense traces should be
kept to a minimum) and away from noise sources (such
as the transmit coil) to minimize error. The gain resistor
R
IN
and filtering capacitor C
IF
should be placed close to
the LTC4125, so that the filtered high impedance lines do
not need to travel far before reaching the IS
+
and IS
–
pins.
The decoupling capacitors C
IN
, C
IN1
and C
IN2
must be
placed as close to the LTC4125 as possible. This allows
as short a route as possible (minimized inductance) from
these capacitors to the respective IN pins and the GND pins
of the part. Figure 18 indicates in blue and green the hot
current loops flowing through C
IN1
, IN1, SW1 and GND;
as well as through C
IN2
, IN2, SW2 and GND. The physi-
cal layout of these hot current loops should be made as
small as possible to minimize parasitic resistance as well
as inductance in the loop. Although the inductance of the
trace between the LTC4125 and the transmit coil does not
matter, the resistance does. Use a trace that is the shortest,
and has maximum available copper thickness and width.
Last but not least, the amount of current flowing in the
transmit coil can be significant. This current also flows
through the switches in the LTC4125. For an applica-
tion with a high quality factor transmit coil and resonant
capacitor, it is not rare to have current upward of 2.5A
RMS. At 2.5A, the power dissipation in the LTC4125 is
approximately 1.25W (in a full bridge setup, the current
always flows through two switches ~ 0.2Ω). With a
θ
JA
of 43°C/W, the LTC4125 part will operate at roughly 55°C
above ambient temperature.
In order to ensure that these quoted thermal resistance
numbers are realized, the following good layout practices
should be followed: use the maximum copper weight in
the board layers as practically and economically possible,
place the recommended number of vias connected to the
exposed pad of the part (refer to LTC Application Notes
for thermal enhanced leaded plastic packages available
at
), and use the maximum size of GND
plane connected to these vias. For proper operation of the
LTC4125, ensure that other common good board layout
practices are also followed. These include isolating noisy
power and signal grounds, having a good low impedance
C
IF
C
IN1
C
IN2
R
IN
R
IS
R
FB1
C
IN
R
FB2
LTC4125
4125 F18
IS+
IS–
IN
IN1
IN2
SW1
FB
SW2
GND
(PIN 21)
C
TX
C
FB1
L
TX
A
B
C
D
I
IN1
CURRENT LOOP:
IN1
→
SW1
→
LC
→
SW2
→
GND
→
C
IN1
I
IN2
CURRENT LOOP:
IN2
→
SW2
→
LC
→
SW1
→
GND
→
C
IN2
Figure 18. High Voltage Nodes (Red), Kelvin Lines and Hot Current Loops in the LTC4125 Circuit
applicaTions inForMaTion
