Linear Technology DC890B, Быстрый старт, Страница: 4 / 13

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 890B
FastDAACS
4
fault browser. Select documentation for “Reference
Design”.
To download data sheets (requires an internet con-
nection):

Choose
“Download Data Sheets” from the Tools
menu.
All datasheets and Quick Start guides for all products in
the QuickEval-II family are downloaded to the
QuickEval-II program folder and placed in the
dsheets
folder.
OPTIONAL CONNECTIONS TO THE DC890B

In CMOS mode the DC890B can operate from the
USB power, however in LVDS mode, the Spartan-III
FPGA IO ring drivers draw considerable supply cur-
rent to bias the active LVDS terminations.
The
DC890B has provisions for a 5mm power plug for
an external 6V ±0.5V supply. The DC890B auto-
matically detects the presence of external power and
disables the USB power input.

X1: The DC890B has provisions for an external
trigger input, Edge selectable by software. This per-
mits initiating data block capture by an external
event.

J2: A JTAG connector is provided for downloading
custom FPGA software to the board. Grounding pin
3 of J2 automatically puts the FPGA into JTAG pro-
gramming mode.
User developed code can be
loaded into the FPGA without compromising the fac-
tory installed code. JUMPER PINS 4 & 6 OF PIC
Programming connector J1 to disable the microcon-
troller when using custom FPGA code. Refer to the
schematic for further details.
This feature is pro-
vided due to customer requests. Development of
custom code will not be supported by the factory
.

J7 & J8 locations (not installed) provide access to 6
additional FPGA pins for test purposes. These pins
also drive LED indicators useful for debug purposes.
Xilinx provides logic analysis and data collection
features through JTAG via ChipScope.
LED INDICATORS
The DC890B provides system status via 8 LEDs:
LED-1.
TRANSFER û Indicates a USB data transfer
from the QuickEval-II to the PC is in progress.
LED-2.
SEEP û Indicates access of the optional dem-
onstration circuit Serial Electrically Erasable
PROM on select demonstration boards. In-
formation in this SEEP permits QuickEval-II
software to configure the DC890B properly
for the device under evaluation using the auto
detect demo board feature in the Config-
ure/Device Menu.
LED-3.
RST û Indicates assertion of either a hard or
soft reset.
LED-4.
DCM_RDY û In LVDS mode, led 4 blinks to
alert the user that the sample clock is either
not present or outside the required frequency
range (Fin mist be > 50 MHz). A steady on
condition indicates the Digital Clock Module
is locked to the input sample clock. In CMOS
mode LED 4 functions as a Power On/FPGA
programmed Indicator.
LED-5.
RUN ON TRIGGER û Indicates that the
board is set to run on trigger (versus halt on
trigger mode).
LED-6.
DATA_RDY û Indicates completion of data
block acquisition.
LED-7.
RUN û Indicates the board is ARMED to col-
lect a block of data.
LED-8.
TRIGGER û indicates that a trigger was re-
ceived and data collection has started.
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