4
dc2541af
DEMO MANUAL DC2541A
operation
Test Turrets
Test turrets on the DC2541A are provided to connect test
measurement equipment across the main supply (AGND
and VEE), 2-pair configured output (VPORT+ and VPORT–),
and 4-pair configured output (VPORT+, VPORT–, DATA2+
and DATA2–). If using an oscilloscope, connect the scope
probe ground leads to a common point or use isolated
differential probes for multiple channels with different
ground references.
RESET
The DC2541A pushbutton switch (SW1) momentarily con-
nects the LTC4279
RESET
pin to VEE when pushed and
released. When the
RESET
pin is logic low, the LTC4279
is held inactive with the port off. When the
RESET
pin is
released logic high, the LTC4279 restarts normal opera-
tion. An external RC network at the LTC4279
RESET
pin
on the DC2541A provides a power turn-on delay.
MID
The DC2541A MID jumper (JP3) ties the LTC4279 MID
pin high to the AGND_P node or low to VEE. When MID
is high, the LTC4279 acts as a midspan device with the
Midspan Mode Detection Backoff timer enabled. When
MID is low, the LTC4279 acts as an endpoint device with
the Midspan Mode Detection Backoff timer disabled. The
LTC4279 MID pin is internally pulled down to VEE if the
shunt at JP3 is removed.
DUALPD
The DC2541A DUALPD jumper (JP4) ties the LTC4279
DUALPD pin high to the AGND_P node or low to VEE.
When DUALPD is high, the LTC4279 detects, classifies
and powers dual-signature PDs. Valid dual-signature PDs
are present when two Type 2 PD signatures are detected
and classified in parallel. PWRMODE must be set to 52.7W
or greater. When the LTC4279 DUALPD pin is low, dual-
signature PD support is disabled. The LTC4279 DUALPD
pin is internally pulled down to VEE if the shunt at JP4 is
removed. Warning: Dual-signature detect, class and power
on is not IEEE 802.3at compliant.
LEGACY
The DC2541A LEGACY jumper (JP5) ties the LTC4279
LEGACY pin high to the AGND_P node for enabling LEGACY
mode, or low to VEE for disabling LEGACY mode. See the
LTC4279 data sheet for further details on LEGACY mode.
The LTC4279 LEGACY pin is internally pulled down to VEE
if the shunt at JP5 is removed. Warning: Legacy detect is,
by definition, not IEEE compliant.
Logic Pin Protection
The DC2541A has a 100Ω resistor (R6, R7 and R8) in
series from each of the LTC4279 logic pins (MID, DUALPD
and LEGACY) and to their respective jumpers (JP3, JP4
and JP5). These resistors provide current limit protection
against high voltage transients when moving the shunt
position at the jumper. In the end application, if the logic
pin is hard tied high to the LTC4279 AGND pin or hard
tied low to VEE, this resistor is not required.
Fuse
A fuse is not a requirement of the LTC4279, however, some
end applications may require one to meet safety require-
ments. The DC2541A fuse (F1) provides a suggested fuse
location and component value.
Surge Protection
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect
the application against damage, protection components are
required at the main supply, at the LTC4279 supply pins,
and at the output port. On the DC2541A, a bulk transient
voltage suppression diode (D2) and a bulk capacitance
(C5) are across the main PoE supply and absorb a majority
of the surge energy coming in to the LTC4279. In the end
