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dc1717afa
DEMO MANUAL DC1717A
Design proceDure for moDification of Dc1717a
operating principles
The other driving mode of the P-channel MOSFETs is used
in the voltage switching operation, when the higher priority
rail replaces the rail losing validity. The gate driver oper-
ates with a fixed current, which is defined by the external
component parameters R
S
and C
S
shown in Figure 1.
The LTC4417 circuit designer should select the value of
R
S
and C
S
based on the MOSFET parameters, power rail
source characteristics, acceptable output voltage droop
during transient, and the value of load capacitance.
C
IN1
68µF
C
S
VS1
LTC4417
G1
V
OUT
V
OUT
R
S
D
S
BAT54
12V WALL
ADAPTER
V1
IRF7324
M1
M2
+
C
L
47µF
+
C
VS1
Figure 1
The valid input range for any supply is controlled by the
OV and UV comparators with resistive dividers (R4-R13).
See the LTC4417 data sheet for design equations to select
resistors to match a particular requirement.
Dual MOSFETs, Q1-Q3, may be replaced with single devices
Q4-Q9 by simply removing Q1-Q3. Pads for Q4-Q9 are
located on the bottom side of the board.
The requirement for AVI may be eliminated by removing
jumpers JP2 and JP3, and removing resistor R19. This
modification leaves the LEDs unpowered and the inputs
of U2 and U3 clamp the
VALID
pins at 0.7V, but otherwise
leaves the LTC4417 operating autonomously.
The following design considerations and equations dem-
onstrate the interrelation of the main component values
and transient parameters in the rail transitions, when the
output voltage exceeds 0.7V. The variables C
S
and R
S
used in the design equations correspond to the following
board components:
•
C20, R23 for V1 (+12V channel)
•
C21, R26 for V2 (+5.0V channel)
•
C22, R28 for V3 (+8.0V channel)
To have dominant influence on the transient time C
S
should
be at least ten times larger than the P-channel MOSFET’s
reverse transfer capacitance (Miller). In this design, for
all rails, C
S
(C20, C21,and C22) equals 47nF.
The slew rate of the output voltage can be expressed as
a function of C
S
:
dV
OUT
dt
=
dV
CS
dt
=
V
SINK
– | V
THRES
|
R
S
•
C
S
(1)
where:
•
V
SINK
is the LTC4417 parameter rated in the data sheet
as
∆
V
G(SINK)
= 4.5V-6V.
•
V
THRES
is the P-channel gate threshold voltage, which
is between –1.5V and –3.5V for the Si7905DN installed
on the board.
•
R
S
= 249Ω and C
S
= 47nF.
Given that dV
OUT
/dt is based on the transient time require-
ment, it is possible to define R
S
from equation 1.
The output voltage slew rate, dV
OUT
/dt, range for the circuit
with the listed parameters is between 85V/ms and 385V/ms.
During the transition of rails, the load can be disconnected
from any rail for a time:
T
DISCON
= t
G(SWITCHOVER)
+ t
pVALID(OFF)
+ t
GATE_THRES
Two first summands of the T
DISCON
are rated in the LTC4417
data sheet as:
t
G(SWITCHOVER)
= (0.3 to 3)µs
t
pVALID(OFF)
= (5 to 13)µs
