1
dc1281af
DEMO MANUAL DC1281A
DESCRIPTION
LTC2209
16-Bit, 160Msps/180Msps/
185Msps ADCs
Demonstration circuit 1281A supports a family of 16-
bit 160Msps/180Msps/185Msps ADCs. Each assem-
bly features one of the following devices: LTC
®
2209,
LTC2209#3BC, or LTC2209#3CD high speed, high dynamic
range ADC.
Other members of this family include the LTC2208 which
is a 130Msps 16-bit version of this device. The LTC2208 is
supported on the DC854 (CMOS) and the DC996 (LVDS).
Lower speed, single-ended clock versions are also sup-
ported on the DC918 and DC919.
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks; QuikEval
and PScope are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
PERFORMANCE SUMMARY
Several versions of the 1281A demo board supporting
the LTC2209 16-bit series of A/D converters are listed in
Table 1. Depending on the required resolution, sample rate
and input frequency, the DC1281A is supplied with the
appropriate ADC and with an optimized input circuit. The
circuitry on the analog inputs is optimized for analog input
frequencies below 80MHz or from 80MHz to 160MHz. For
higher input frequencies, contact the factory for support.
Design files for this circuit board are available at
http://www.linear.com/demo
(T
A
= 25°C)
Table 1. DC1281A Variants
DC1281A VARIANTS
ADC PART NUMBER
RESOLUTION
MAXIMUM SAMPLE RATE
INPUT FREQUENCY
SUPPLY VOLTAGE
1281A-A
LTC2209
16-Bit
160Msps
1MHz to 80MHz
3.3V
1281A-B
LTC2209
16-Bit
160Msps
80MHz to 160MHz
3.3V
1281A-E
LTC2209#3BCPBF
16-Bit
180Msps
1MHz to 80MHz
3.6V
1281A-F
LTC2209#3BCPBF
16-Bit
180Msps
80MHz to 160MHz
3.6V
1281A-G
LTC2209#3CDPBF
16-Bit
185Msps
1MHz to 80MHz
3.6V
1281A-H
LTC2209#3CDPBF
16-Bit
185Msps
80MHz to 160MHz
3.6V
PARAMETER
CONDITION
VALUE
Supply Voltage – LTC2209
Depending on Sampling Rate and the A/D Converter Provided, This Supply Must
Provide Up to 700mA.
Optimized for 3.3V
[3.15V
⇔
3.45V min/max]
Supply Voltage – LTC2209#3BC
and LTC2209#3CD
Depending on Sampling Rate and the A/D Converter Provided, This Supply Must
Provide Up to 700mA.
Optimized for 3.6V
[3.5V
⇔
3.78V min/max]
Analog Input Range
Depending on PGA Pin Voltage
1.5V
P-P
to 2.25V
P-P
Logic Input Voltages
Minimum Logic High
Maximum Logic Low
2V
0.8V
Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load)
Minimum Logic Levels (100Ω Load)
350mV/2.1V Common Mode
247mV/2.1V Common Mode
Sampling Frequency (Convert
Clock Frequency)
See Table 1
Convert Clock Level
50Ω Source Impedance, AC-Coupled or Ground Referenced (Convert Clock Input Is
Capacitor Coupled on Board and Terminated with 50Ω).
2V
P-P
⇔
2.5V
P-P
Sine Wave or
Square wave
Resolution
See Table 1
Input Frequency Range
See Table 1
SFDR
See Applicable Data Sheet
SNR
See Applicable Data Sheet
