LTC3882-1
59
Rev A
Figure 41. Normalized RMS Input Ripple Current
Figure 42. Normalized Output Ripple Current [I
RMS
~ 0.3(DI
C(PP)
)]
0
0.1
0.2
0.3
0.4
38821 F41
0.5
0.6
DUTY FACTOR (V
OUT
/V
IN
)
0.1
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.3
0.5 0.6
0.2
0.4
0.7 0.8 0.9
1-PHASE
2-PHASE
DUTY FACTOR (V
OUT
/V
IN
)
0.1
DI
C(P-P)
V
O
/L
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.3
0.5 0.6
38821 F42
0.2
0.4
0.7 0.8 0.9
1-PHASE
2-PHASE
Figure 40. Single and 2-Phase Current Waveforms
38821 F40
SW1 V
I
CIN
I
COUT
SINGLE PHASE
SW1 V
SW2 V
I
CIN
I
L2
I
L1
I
COUT
DUAL PHASE
RIPPLE
synchronized time-based rail sequencing and ramping and
report accurate output current telemetry for all phases.
In general, only the PGOOD pin of the master phase needs
to be used for external Power Good indication. However,
APPLICATIONS INFORMATION
PGOOD pins of slave phases may be shorted to a master
PGOOD bus to indicate full output power is available, un-
less the slave channel is used in active phase shedding.
In that case, the slave PGOOD should be left disconnected
or used only to indicate operating status for that phase.
Output current fault and warning limits should each be set
to the same values across all PolyPhase channels using
IOUT_FAULT_LIMIT and IOUT_WARN_LIMIT. The cor-
rect sense resistance and related temperature coefficient
should also be set for each phase (IOUT_CAL_GAIN,
MFR_IOUT_CAL_GAIN_TC) to achieve accurate I
OUT
telemetry and consistent fault handling across phases.
Because the LTC3882-1 current sharing loop operates by
matching sensed voltage, it is important that well-matched
sense elements be used in the system. Current matching
parameters specified for the LTC3882-1 do not include these
external sources of error, such as inductor DCR tolerance.
Programming of V
OUT
related parameters is not required
for slave phases.
A PolyPhase power supply significantly reduces the amount
of ripple current in both the input and output capacitors.
The RMS input ripple current is divided by, and the ef-
fective ripple frequency is multiplied by, the number of
phases used as long as the input voltage is greater than
the number of phases used times the output voltage. The
output ripple amplitude is also reduced by the number of
phases used. Figure 40 graphically illustrates the principle.
The worst-case RMS ripple current for a single stage de-
sign peaks at an input voltage of twice the output voltage.
The worst case RMS ripple current for a 2-phase design
peaks at output voltages of 1/4 and 3/4 of the input volt-
age. When the RMS current is calculated, higher effective
duty factor results and the peak current levels are divided
as long as the current in each stage is balanced. Refer to
Application Note 19 at http://www.linear.com/designtools/
app_notes for a detailed description of how to calculate
RMS current for the single stage switching regulator. Fig-
ure 41 and Figure 42 illustrate how the input and output
currents are reduced by using an additional phase. For a
2-phase converter, the input current peaks drop in half and
the frequency is doubled. The input capacitor requirement
is then theoretically reduced by a factor of four.
