LMS7002M Quick Starter Manual for EVB7 kit
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P a g e
Version: 2.2
Last modified: 29/09/2014
RX TSP B
RX TSP B clock delay. Clock can be delayed by 200 ps, 500 ps, 800 ps and 1100 ps. By
default clock delayed 200 ps.
RX TSP A
RX TSP A clock delay. Clock can be delayed by 200 ps, 500 ps, 800 ps and 1100 ps. By
default clock delayed 200 ps.
TX LML B
TX LML B clock delay. Clock can be delayed by 400 ps, 500 ps, 600 ps and 700 ps. By
default clock delayed 400 ps.
TX LML A
TX LML A clock delay. Clock can be delayed by 400 ps, 500 ps, 600 ps and 700 ps. By
default clock delayed 400 ps.
RX LML B
RX LML B clock delay. Clock can be delayed by 200 ps, 500 ps, 800 ps and 1100 ps. By
default clock delayed 200 ps.
RX LML A
RX LML A clock delay. Clock can be delayed by 200 ps, 500 ps, 800 ps and 1100 ps. By
default clock delayed 200 ps.
BIST
7.20
The Build-In Self-Test (BIST) modules for SXT, SXR and CGEN controls are described in this
chapter.
Figure 45 GUI BIST tab
The BIST modules are used for the test proposes only. There is one test vector generator which
supplies the test vectors for CGEN, SXT and SXR modules. After pressing the ‘Read BIST’
button the test results (test vector signature) will be displayed for the selected block.
A picture of the tab is shown in
. A description of each function available in this tab is
shown below in Table 22.
Table 22 GUI BIST control description
Parameter
Description
