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Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
F. System Control Subsystem
The SYSCON resides at the top level of the circuit architecture and is responsible for clock
generation and clock and reset distribution within the digital baseband controller, as well as
to external devices.
The block is a slave peripheral under control of the ARM processor. The programming of the
SYSCON controls the fundamental modes of operation within the digital baseband controller.
Individual blocks can also be reset and their clocks held inactive by accessing the
appropriate control registers.
3.1.4 RF Interface
A. DB3200 Interface
DB3200 controls GSM RF part using these signals through GSM RF chip-Gimli.
y
RF_DATA_A
y
RF_DATA_B
y
RF_DATA_C
y
RF_DATA_STRB
Figure 3-1- 5. Schematic of DB3200 RF Interface
B. WCDMA Radio Link Interface
y
RF_WCDMA_PA_0_EN
y
RF_WCDMA_PA_1_EN
y
RF_WCDMA_DCDC_EN
y
RF_WCDMA_PWRDET_EN
Figure 3-1-6. Schematic of WCDMA RF Interface
D15
TX_ADC_STRB
B15
RF_DATA_A
RF_DATA_B
B16
RF_DATA_C
C15
IDATA_FREQ_MSB
QDATA_AMP_MSB
TX_ADC_STRB
AMP_FREQ_LSB
C13
RF_WCDMA_PWRDET_E
D15
TX_ADC_STRB
TX_POW
B6
B15
RF_DATA_A
RF_DATA_B
B16
RF_DATA_C
C15
RF_DATA_STRB
A16
RF_WCDMA_DCDC_EN
B13
RF_WCDMA_PA_0_EN
B14
D14
RF_WCDMA_PA_1_EN
ADC_I_NEG
D9
ADC_I_POS
C9
C8
ADC_Q_NEG
ADC_Q_POS
D8
WPOW_DET_EN
DATA_STR
IDATA_FREQ_MSB
QDATA_AMP_MSB
WRX_Q_N
WRX_I_P
WRX_I_N
WRX_Q_P
TX_ADC_STRB
WTX_BAND_2_EN
WTX_BAND_5_EN
AMP_FREQ_LSB
WPOW_DET
Содержание TU750
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