LG TU550, Руководство по обслуживанию

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3. TECHNICAL BRIEF
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Most UMTS Rx PLL circuits are included within the RTR6250 IC: reference divider, phase detector,
charge pump, feedback divider, and digital logic that generate LOCK status. The buffered 19.2 MHz
TCXO signal provides the synthesizer input (REF), the frequency reference to which the PLL is phase
and frequency locked. The reference is divided by the R-Counter to create a fixed frequency input to
the phase detector, FR. The other phase detector input (FV) varies as the loop acquires lock, and is
generated by dividing the RX_VCO_IN frequency using the feedback path.s N-Counter. The closed
loop will force FV to equal FR when locked. If the loop is not locked the error between FV and FR will
create an error signal at the output of the charge pump. This error signal is filtered by the loop filter
and applied to the VCO, tuning the output frequency such that the error is decreased. Ultimately the
loop forces the error to approach zero and the PLL is phase and frequency locked.
Many key PLL performance characteristics are largely determined by the loop filter design - stability,
transitory response, settling time, and phase noise.
3.4.2 Transceiver PLL (PLL1)
All LO functional blocks for the other handset modes(UMTS Tx, GSM850/GSM900 Tx/Rx, DCS Tx/Rx,
PCS Tx/Rx) are integrated into the RTR6250 IC except the loop filter components (Figure 3.4.2-1).
On-chip circuits include reference divider, phase detector, charge pump, VCO, feedback divider, and
digital logic status. The functional description given in Section 3.4.1 for the UMTS Rx PLL applies to
the Transceiver PLL as well.
The off-chip loop filter allows optimization of key PLL performance characteristics (stability, transitory
response, settling time, and phase noise) for different applications. Guidelines are provided in the next
subsection for proper implementation of this critical circuit.
Figure 3.4.2-1 Transceiver PLL functional block diagram