- 2-20 -
■
IC503 M12L16161A
1) PORT ASSIGNMENT
2) BLOCK DIAGRAM
CLK
ADD
LCKE
LRAS
LCBR
LWE
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LDQM
LWCBR
LCAS
Bank Select
LWE
LDQM
DQI
Data Input Regidter
512K x 16
512K x 16
Column Decoder
Latency & Burst Length
Programming Register
Timing Register
Address Register
Ro
w Decoder
LCBR
LRAS
Sense AMP
I/O Control
Output Buff
er
Col.
Buff
er
Ro
w Buff
er
Refresh Counter
Содержание TCH-M550
Страница 8: ... 2 3 ...
Страница 9: ... 2 4 ...
Страница 10: ... 2 5 ...
Страница 11: ... 2 6 ...
Страница 12: ... 2 7 ...
Страница 13: ... 2 8 ...
Страница 14: ... 2 9 ...
Страница 15: ... 2 10 ...
Страница 21: ... IC501 MN6627933 1 PORT ASSIGNMENT 2 16 ...
Страница 22: ... 2 17 2 Block Diagram ...
Страница 27: ... 2 22 IC505 AMC1117 BLOCK DIAGRAM ...
Страница 29: ... 2 24 IC801 TA8275H IC901 LC75811 ...
Страница 31: ... SCHEMATIC DIAGRAM MAIN SCHEMATIC DIAGRAM 2 27 2 28 ...
Страница 32: ...2 29 2 30 FRONT SCHEMATIC DIAGRAM ...
Страница 33: ...2 31 2 32 CDP SCHEMATIC DIAGRAM ...
Страница 35: ... MAIN P C BOARD 2 35 2 36 ...
Страница 36: ...2 37 2 38 CDP P C BOARD CDP P C BOARD ...