LG MX8550, Руководство по обслуживанию

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M X8550
2.3.7 DSP (Multimedia processor) Part
DSP is a specialized integrated circuit that encompasses efficient camera functions, MPEG4 simple profile level 3
compliant codec functions. The host’s register setting by executed with 2-bit address bus, 1-bit chip select signal, 1-
bit write enable signal, 1-bit read enable signal and 16-bit data bus from the host(MSM6500). DSP contained the
advanced ARM9. ARM9 is a member of the ARM family of general-purpose 32-bit microprocessors.
LCD
In the bypass mode, MSM has complete control over all LCD operations, excluding camera processing function. In
other words, it indicates when LCD is initialized and GUI of system is displayed on the LCD.
CAMERA
DSP provides clock to operate sensor and controls internal register of sensor through the I2C master embedded in
DSP to make sensor operate normally. After completion of internal register setting, sensor supplies YUV422 image
data, synchronous signal and pixel clock synchronized with pixel of image data to DSP. VSYNC is a synchronized
signal to differentiate frames and HREF is a synchronized signal to differentiate lines. These signals are synchronized
with the pixel clock. Input image data through the sensor interface is previewed on the LCD up to 30fps through the
IMAGE ENHANCER.
EXTERNAL CODEC
Normally codec bypass signal from MSM6500 to Speaker, Receiver or Headset. However, when we listen to the
music in “My Music” folder codec performs 3-D sound enhancement and automatic level control for microphone or
line input. The on-chip ADC and DAC are of a high quality using a multi-bit, low-order oversampling architecture to
deliver optimum performance with low power consumption. It supports I2S audio data format between DSP and
codec. A speaker amplifier, using digital amplifier system, realizes low power consumption than that of linear
amplifier. In addition, power-down mode is available to minimize the current consumption when used.
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