- 141 -
Copyright © 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
8. CIRCUIT DIAGRAM
26MHz
X201
TSX-3225
2
1
3
4
GND2
HOT2
HOT1
GND1
VDDTRX
1n
C232
C235
47p
47p
C237 C236
47p
47p
C234
C228
47p
47p
C227
C226
DNI
C225
DNI
VDD_IO_1V8
1n
C233
VMIC_BIAS_P
CN201
9
8
7
6
5
4
3
2
1
C239
220n
18p
C240
C241
18p
2.2K
R218
R217
2.2K
VDD_IO_1V8
10K
R213
100K
R214
100K
R215
2V85_VSIM
0.1u
C224
VUSB_CHG_IN
4.7n
C223
75
FB201
I
N
D
60
2
R
VBAT
VBACKUP_BAT
VRF1
VDDRF2
VUSB
VMMC_2V85
VPA_2V85
VBAT_RF2
VPMU
VDD_IO_1V8
VDD_IO_1V8
VDD_IO_1V8
VDD_IO_1V8
VBAT
10u
C222
R216
4.7K
VAUD_HS_BIAS
R211
24K
22u
C221
R205
5.6K
3.9K
R203
VDDXO
VBAT
L201
3.3u
R204
100K
Q202
2
1
3
VDDMS
470n
C238
Q201
2
1
3
VCORE
R202
470
VDD_IO_1V8
C231
330p
OJ201
OJ203
TP204
VBAT
UA201
12
11
10
9
8
7
6
5
4
3
2
1
GND
RX
TX
NC1
ON_SW
VBAT
NC2
NC3
NC4
DSR
RTS
CTS
GND
RX
TX
VCHAR
ON_SW
VBAT
PWR
URXD
UTXD
3G
2.5G
R208
12K
R209
100K
D201
C230
470n
C229
1u
R212
270
VDDTDC
5.1
R210
TP201
VDD_IO_1V8
L202
22n
TP203
VDD_IO_1V8
TP202
VDD_IO_1V8
2.2u
C202
VDD_IO_1V8
VDD_IO_1V8
VUSB
VBAT
0
10
2
R
VCORE
VDDMS
VDDTRX
VDD_IO_1V8
0.1u
C216
VDD_IO_1V8
VDDRF2
VDDTDC
VMMC_2V85
VDD_IO_1V8
VRF1
0.1u
C206
VPA_2V85
C203
0.1u
C214
1u
VDDXO
C211
4.7n
C205
470n
VBAT_RF2
C219
470n
C213
47n
C212
47n
VPMU
C217
0.1u
VBAT
1u
C208
0.1u
C201
C207
220n
C210
220n
C204
470n
C209
18p
1u
C215
C218
1u
PMB8815
U201
8
K
7
T
8
R
9
M
6
T
8
M
8
L
2
1
L
7
1
C
7
1
F
2
1
H
5
1
G
1
1
M
9
L
4
1
F
0
1
P
4
1
E
6
1
G
8
1
R
4
1
B
3
1
E
5
1
H
4
1
G
5
1
A
2
1
J
5
1
F
6
1
F
7
1
P
6
1
P
0
1
G
0
1
K
7
R
1
1
J
1
1
H
0
1
F
3
A
1
1
T
2
1
P
8
H
6
P
6
F
9
K
1
1
G
0
1
N
8
1
P
3
1
L
6
1
L
9
R
9
T
8
T
9
P
T12
P13
R12
P15
P14
T15
R15
T14
R14
N17
N18
T16
R16
M18
M17
K17
P11
P4
J4
T2
J5
G1
L4
J3
L2
P5
P2
J8
T5
P1
T4
R6
R2
N2
B1
A2
G6
H4
H2
G2
G3
H3
H1
H6
K4
K2
J1
K3
L3
J2
M2
L1
M3
R1
P7
N6
N4
L5
M5
T3
R4
R3
P3
M1
M4
N3
N5
R5
L11
K12
L10
G12
H13
J13
F13
G13
C6
J14
J15
K18
H17
H18
G18
J18
J17
H14
E1
G4
G5
F2
F3
F1
D2
D1
E2
M10
A13
B13
K14
K13
B4
A5
B5
A4
J10
H9
J9
H10
B16
C14
B17
B18
C15
B15
C16
E18
F18
C18
D18
A16
A17
R17
T17
M13
M12
N13
R13
T13
N14
1
1
F
1
T
8
1
T
8
1
A
1
A
1
1
R
7
A
7
B
0
1
C
0
1
B
0
1
A
0
1
D
6
B
5
1
L
7
1
L
8
1
L
6
A
0
1
R
0
1
T
2
1
F
1
1
E
1
1
C
1
1
B
1
1
D
2
1
E
2
1
D
2
1
C
2
1
B
2
1
A
1
1
A
8
E
9
G
8
F
9
E
9
F
8
G
0
1
E
9
C
8
C
9
B
9
A
7
C
8
B
8
A
2
B
2
C
4
E
6
D
5
C
5
E
5
F
1
C
4
D
3
B
3
C
4
C
5
D
4
F
3
D
3
E
0
D
_
F
I
D
1
D
_
F
I
D
2
D
_
F
I
D
3
D
_
F
I
D
4
D
_
F
I
D
5
D
_
F
I
D
6
D
_
F
I
D
7
D
_
F
I
D
8
D
_
F
I
D
1
S
C
_
F
I
D
D
C
_
F
I
D
R
W
_
F
I
D
D
R
_
F
I
D
D
H
_
F
I
D
D
V
_
F
I
D
T
E
S
E
R
_
F
I
D
0
D
_
F
I
C
1
D
_
F
I
C
2
D
_
F
I
C
3
D
_
F
I
C
4
D
_
F
I
C
5
D
_
F
I
C
6
D
_
F
I
C
7
D
_
F
I
C
K
L
C
P
_
F
I
C
C
N
Y
S
H
_
F
I
C
C
N
Y
S
V
_
F
I
C
2
T
U
O
K
L
C
D
P
_
F
I
C
T
E
S
E
R
_
F
I
C
0
N
I
_
P
K
1
N
I
_
P
K
2
N
I
_
P
K
3
N
I
_
P
K
4
N
I
_
P
K
5
N
I
_
P
K
0
T
U
O
_
P
K
1
T
U
O
_
P
K
2
T
U
O
_
P
K
3
T
U
O
_
P
K
5
T
U
O
_
P
K
B
I
V
B
I
V
_
S
S
V
0
T
U
O
K
L
C
K
2
3
F
K
2
3
C
S
O
N
_
T
E
S
E
R
N
I
2
T
0
K
L
C
_
1
S
2
I
X
R
_
1
S
2
I
X
T
_
1
S
2
I
0
A
W
_
1
S
2
I
L
C
S
_
C
2
I
A
D
S
_
C
2
I
F
F
O
N
O
1
C
N
2
C
N
3
C
N
4
C
N
S
F
D
D
V
M0
M1
M2
VDD_FMR
FMRIN
FMRINX
CP1
CP2
TX1
FE2
RX12
RX12X
RX34
RX34X
VDET
PABS
PABIAS
FE1
TX2
PAEN
VDDTRX
USIF2_TXD_MTSR
USIF2_RXD_MRST
USIF2_RTS_N
USIF2_CTS_N
USIF1_TXD_MTSR
USIF1_RXD_MRST
USIF1_RTS_N
USIF1_CTS_N
DPLUS
DMINUS
XOX
XO
VSIM
SIM_IO
SIM_CLK
SIM_RST
MMCI_CMD
MMCI_DAT_0
MMCI_CLK
MMCI_DAT_1
MMCI_DAT_2
MMCI_DAT_3
SWIF_TXRX
TDO
TDI
TMS
TCK
TRST_N
TRIG_IN
MON1
MON2
MON3
FSYS1
FSYS2
DIGUP_CLK
DIGUP1
DIGUP2
LEDFBN
LEDFBP
LEDDRV
A_D0
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_D8
A_D9
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
FWP
FCDP_RBn
CS0_n
CS1_n
CS2_n
ADV_n
RD_n
WR_n
WAIT_n
RAS_n
CAS_n
BC0_n
BC1_n
BC2_n
BC3_n
SDCLKO
BFCLKO_0
BFCLKO_1
CKE
ANAMON
FSYS_EN
EPN
EPP
HSL
HSR
LSN
LSP
MICN1
MICP1
MICN2
MICP2
VMIC
VUMIC
ACD
AGND
VREF
1
D
S
_
D
D
V
B
F
_
1
D
S
1
D
S
_
S
S
V
W
S
1
D
S
1
S
M
S
S
V
2
S
M
S
S
V
P
S
T
A
B
V
U
M
P
_
T
A
B
V
1
O
I
D
D
V
2
O
I
D
D
V
1
U
B
E
_
D
D
V
2
U
B
E
_
D
D
V
L
L
D
_
D
D
V
U
M
P
V
U
M
P
_
S
S
V
1
E
R
O
C
S
S
V
2
E
R
O
C
S
S
V
3
E
R
O
C
S
S
V
4
E
R
O
C
S
S
V
5
E
R
O
C
S
S
V
E
R
O
C
V
E
R
O
C
D
D
V
P
C
8
V
1
D
D
V
R
S
L
S
S
V
X
R
T
S
S
V
X
R
S
S
V
1
8
V
1
D
D
V
P
M
A
R
V
G
I
D
_
S
S
V
S
M
D
D
V
O
X
D
D
V
C
D
T
D
D
V
G
E
N
D
D
V
T
A
B
V
O
C
D
S
S
V
X
U
A
V
O
X
S
S
V
C
M
M
V
B
S
U
V
2
F
R
D
D
V
1
F
R
V
O
L
_
S
S
V
F
R
S
S
V
C
T
R
V
N
E
S
N
E
S
P
E
S
N
E
S
G
H
C
D
D
V
S
C
B
S
C
G
H
C
V
T
N
H
S
V
CM315_12_5PF
X202
32.768KHz
2
1
BAT201
SMZY0023501
C220
0.1u
4.7K
R207
VBACKUP_BAT
]0[
AT
A
D_
M
A
C
]1[
AT
A
D_
M
A
C
]2[
AT
A
D_
M
A
C
]3[
AT
A
D_
M
A
C
]4[
AT
A
D_
M
A
C
]5[
AT
A
D_
M
A
C
]6[
AT
A
D_
M
A
C
]7[
AT
A
D_
M
A
C
C
N
Y
S
H_
M
A
C
KL
C
P_
M
A
C
C
N
Y
S
V_
M
A
C
KL
C
M_
M
A
C
S
R_
D
CL
FM_ANT
HS_MIC_N
USB_DP
USB_DM
PWRON
PWRON
UART_TX
UART_TX
UART_TX
SIM_DATA
SIM_CLK
HS_MIC_P
MSD_CLK
N_
T
E
D_
D
S
M
MSD_D[1]
MSD_D[0]
MSD_CMD
MSD_D[3]
MSD_D[2]
MAIN_MIC_P
N_
S
C_
D
CL
DDR_CAS_N
DDR_RAS_N
DDR_DQS[1]
DDR_DQS[0]
DDR_DQM[0]
DDR_DQM[1]
NAND_BSY_N
NAND_CS_N
DDR_D[15]
DDR_D[05]
DDR_D[01]
DDR_D[02]
DDR_D[00]
DDR_D[14]
DDR_D[13]
DDR_D[12]
DDR_D[11]
DDR_D[10]
DDR_D[09]
DDR_D[08]
DDR_D[07]
DDR_D[06]
DDR_D[04]
DDR_D[03]
BT_UART_TX
BT_UART_RX
UART_RX
UART_RX
UART_RX
VUSB_LDO_4V9
ST
R_
T
R
A
U_
T
B
ST
C_
T
R
A
U_
T
B
RF_HB_TX
RF_LB_TX
RF_HB_RXN
RF_LB_RXP
RF_TX_EN
BAT_TEMP
BT_PCM_SYNC
T
U
O_
M
C
P_
T
B
NI
_
M
C
P_
T
B
BT_PCM_CLK
T
U
O_
C
N
Y
S
V_
D
CL
P
U
E
K
A
W_
T
B
K2
3_
CT
R
LCD_RST_N
BT_CLK_26M
BT_RST_N
T
S
O
H_
P
U
E
K
A
W_
T
B
BT_CLK_REQ
I2C_SDA
I2C_SCL
N
D
W
P_
M
A
C
N_
T
S
R_
M
A
C
SPI_CLK
SPI_MISO
SPI_INT
S
C
_
I
P
S
SPI_MOSI
]3[
T
U
O_
Y
E
K
]3[
NI
_
Y
E
K
]2[
T
U
O_
Y
E
K
N_
R
W_
D
CL
N_
T
E
S
E
R
RESET_N
JTAG_TRST_N
JTAG_TRST_N
JTAG_TDI
JTAG_TDI
JTAG_TMS
JTAG_TMS
JTAG_TCK
JTAG_TCK
JTAG_TDO
JTAG_TDO
P_
BI
V
]7
0[
D_
D
CL
]6
0[
D_
D
CL
]5
0[
D_
D
CL
]4
0[
D_
D
CL
]3
0[
D_
D
CL
]2
0[
D_
D
CL
]1
0[
D_
D
CL
]0
0[
D_
D
CL
N_
T
NI
_
CI
U
M
F_BOOT
F_BOOT
]1[
NI
_
Y
E
K
HS_JACK_DET
SPK_HS_L
SPK_HS_R
WLAN_REG_ON
RF_ANT_SEL[0]
RF_ANT_SEL[1]
RF_TX_RAMP
RF_HB_RXP
RF_LB_RXN
FM_LNA_EN
F_MODE
F_MODE
FM_ANT_2
FM_ANT_2
T
E
D_
K
O
O
H_
S
H
T
NI
_
H
C
U
OT
DI
_
R
E
K
A
M_
D
CL
L
E
S
_
T
S
R
_
M
I
S
SIM_SEL
NAND_DDR_WE_N
NANDD_DDRA[00]
NANDD_DDRA[01]
NANDD_DDRA[10]
NANDD_DDRA[11]
NANDD_DDRA[12]
NANDD_DDRA[13]
NANDD_DDRA[14]
NANDD_DDRA[15]
NANDD_DDRA[02]
NANDD_DDRA[03]
NANDD_DDRA[04]
NANDD_DDRA[05]
NANDD_DDRA[06]
NANDD_DDRA[07]
NANDD_DDRA[08]
NANDD_DDRA[09]
DDR_CLK_P
NAND_WP_N
DDR_CKE
NAND_ALE_N
NAND_RE_N
NAND_CLE_N
DDR_CLK_N
DDR_CS_N
SIM_RST_N
MAIN_MIC_N
L
RT
C_
L
B_
D
CL
T
S
R_
H
C
U
OT
RCV_HS_N
RCV_HS_P
S
H_
V
C
R_
L
E
S
VDD_EBU
PIN N10
PIN K9
DBB SUPPLIES
ABB SUPPLIES
PIN_G15
PIN_G16
PIN_E13
PIN_B14
PIN G11
PIN F6,P6
PIN P12
PIN P16
VBAT_PMU
(10V)
RF SUPPLIES (CLEAN GND)
PIN P10
PIN L9
PIN M11
PIN K10
PMU SUPPLIES
RF SUPPLIES (DIRTY GND)
PIN_B16
PIN_H15
VDD_IO1
VDD1V8CP
VBATSP
VDD_IO2
Speaker Supply
Seperate and shield
PIN_H12
(10V)
(1%)
2-5-1-2_IFX_XMM215x_NAND_V0.1
UART PORT
Connect GND plane directly
Close to the 26MHz XTAL
INT PORT
BT_DBB_INT
DIF_RESET
EINT4
USIF1_CTS_N
_CHG_EOC
SLIDE
T2IN
SIGNAL NAME
DIGUP2
MUIC_INT
CC0CC1IO
EINT7
CC1CC6IO
EINT0
PIN NAME
uSD_DET
USIF1_RTS_N
VDDP_EBU
ABB
VDDP_DIG1
1T
NI
E
6T
NI
E
0T
NI
E
0T
NI
E
CT
R_
D
D
V
4T
NI
E
VDDP_DIG1
OI
3
C
C1
C
C
6T
NI
E
VDDP_DIG1
0T
NI
E
1T
NI
E
OI
0
C
C1
C
C
OI
4
C
C0
C
C
OI
4
C
C1
C
C
5T
NI
E
VDDP_SIM
VDDP_MMC
VDDP_DIG1
RF
CC0CC1IO
CC0CC7IO
EINT4/EINT1
VDDP_DIG1
EINT3
EINT2
CC1CC6IO
ABB
RF
VDDP_ULPI
RF
VDDP_DIG2
7T
NI
E
1
GI
D_
P
D
D
V
1
GI
D_
P
D
D
V
4-6-1-1 Super Cap
VDDP_DIG1
FM Radio(LNA)
To Main Chipset!
VDDP_DIG1
VDDP_EBU