2
+1V8_VREG_L5
+VPWR
+1V3_VSW_S3
2
+VPWR
+1V3_VSW_S3
+1V85_VSW_S4
+1V85_VSW_S4
2
+1V3_VSW_S3
+VPWR
+VPWR
2
+VPWR
+VPWR
+VPWR
+VPWR
+1V85_VSW_S4
Place C4214 close to pin# 67
C4215 close to pin# 148
Connect GND from PMIC to input capacitor, then to system GND
2
2
C4218
22u
2
C4233
2
C4224
+1V15_VSW_S5_S6
+3V3_VREG_L9
+1V85_VSW_S4
+1V15_VSW_S2
+1V0_VREG_L1
1
2.2u
1
+1V2_VREG_L2
+1V15_VREG_L3
+1V8_VREG_L4
+1V8_VREG_L6
+2V9_VREG_L8
2
C4222
+1V8_VREG_L7
2
C4234
+2V95_VREG_L11
2
C4220
2
C4221
+2V95_VREG_L12
+3V075_VREG_L13
+2V85_VREG_L14_UIM1
+2V95_VREG_L15_UIM2
+1V3_VSW_S3
1
1
2.2u
+1V8_VREG_L16
+2V8_VREG_L17
+2V85_VREG_L10
+2V7_VREG_L18
+1V35_VREG_L19
2
C4229
+1V2_VREG_L23
2
C4223
VREG_S2_VSENSE
VREG_S5_S6_VSENSE_P
VREG_S1_VSENSE
S2 : MSM8937 (VDD_CORE, VDD_CDC_SDC)
RF(WTR0 , WTR1)
MSM(VDD_QFPROM_PRG, VDD_MIPI_DSI_PLL) / ACCEL_COMPASS(VDD_IO)
MSM(VDD_PLL2, VDD_USB_1P8, VDD_A2)
ACCEL_COMPASS(VDD) / Proximity(VDD)
BT_WIFI
SDCARD(VDD)
MSM(VDD_P2)
MSM(VDD_USB_3P3)
MSM(VDD_P5)
RF(WTR0 , WTR1 , GPS_LNA)
MSM(VDD_P6)
eMMC (VDDQ,VDDCA) / LPDDR3 (VDD2) / MSM (P1 , VDD_USB_CORE , VDD_MIPI_DSI_1P2 , VDD_MIPI_CSI)
eMMC(VCC)
S5, S6 : MSM8937(VDD_APC)
S3 : LDO IN(L1,L2,L3,L19,L23)
MSM (P3, P5, P6, P7) / PM (VDD_AUDIO_IO) / PMI (VDD_MSM_IO, VDD_1P8_DIS_N) / eMMC (VCCQ) / LPDDR3 (VDD1) / Debugger(VDD) / HALL IC(VDD) / PCB Rev. / NFC(I/O)
MAIN_CAM(AF) / RGB / LDAF(VDD)
PM(XO_Therm, PA_Therm)
S4 : LDO IN ( L4,L5,L6,L7,L16,VDD_XO_RFCLK(L20,L21) ), CODEC(VDD_HPH, VDD_CP)
MSM (VDD_MEM, VDD_PLL1, VDD_EBI_CDC)
S1 : MSM8937 (VDD_MODEM)
PSEUDO CAPLESS LDOs
- L4*, L6, L8*, L9*, L10, L11*, L12, L14, L15, L17*, L18, L22, L23
RF(SWITCH)
MSM(VDD_A1, VDD_WLAN)
L4*, L9*, L11*, L17*, still need validation as Pseudo-capless.
VREG_S5_S6_VSENSE_N
2
< PM8940_Power>
2
1
DNI
Star-route from pin #135 and pin #162 to C4216 / C4217
2
C4230
2
2
C4225
C4232
2
L5, L7, L13, L16 have internal PMIC loads and require local CAPs
Y
Y
Output Power Management
3.000 - 3.300 V
3.075 V
300mA
300mA
5mA
5mA
600mA
300mA
1200mA
5mA
50mA
800mA
2500mA
3000mA
2000mA
1.200V
1.800V
1.225V
2.700V
2.850V
1.800V
1.800V
2.950V
1.800V
2.850V
1.800V
1.800V
1.200V
2.050V
1.225V
Circuit
Y
Y
L23
L22
L21
Y
Y
L20
L19
L18
L17
L16
L15
L14
L13
L12
L11
L10
L9
L8
L7
L6
L5
L4
HF-SMPS
L3
L2
ULT-SMPS
L1
Voltage
Rated
On
Range
Programmable
Specified
Default
Current
Range
Default
Type
Function
Low-noise LDO
1.000V
1.225V
1.800V
2.900V
3.3V or 3.0V
2.950V
2.800V
2700mA
1200mA
450mA
150mA
600mA
600mA
150mA
150mA
150mA
300mA
1200mA
Y
0.900 - 1.350 V
0.550 - 1.350 V
1.200 - 1.412 V
1.800 - 2.050 V
1.050 - 1.350 V
0.750 - 1.350 V
1.80V or 2.95V
0.375 - 1.562 V
1.550 - 3.126 V
0.350 - 1.355 V
0.375 - 1.537 V
1.750 - 3.337 V
0.375 - 1.537 V
1.750 - 3.337 V
0.375 - 1.537 V
1.350V
S6
S5
S4
S3
S2
S1
ULT-SMPS
ULT-SMPS
FT-SMPS
FT-SMPS
1.288V
1.225V
1.225V
1.050 - 1.350 V
0.375 - 1.562 V
0.375 - 1.562 V
0.350 - 1.355 V
3000mA
3000mA
Y
Y
Y
Y
NMOS LDO
NMOS LDO
NMOS LDO
NMOS LDO
Low-noise LDO
PMOS LDO
NMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
PMOS LDO
3.075V
1.800V
1.800V
1.200V
1.000V
1.800V
1.800V
1.800V
1.800V
2.900V
2.800V
2.950V
1.80V or 3.30V
1.80V or 3.30V
1.800V
2.850V
1.200V
1.800V
2.700V
2.800V
1.350V
1.800V
0.375 - 1.537 V
0.375 - 1.537 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1.750 - 3.337 V
1200mA
50mA
50mA
Y
N
Y
Y
Y
* The above table is based on PM8937.
(80-P2564-1).
MAIN_CAM(DVDD)
Y
Y
L4204
1
Place C4212 closer to PMIC
L4205
1
C4231
2
2
C4226
R4205
2
1
0
+2V8_VREG_L22
2
2
C4240
2.2u
2
1
2
Rev.B 3/15
2
C4227
2
C4228
2
C4241
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
L
K
J
I
H
G
F
E
D
C
B
A
L
K
J
I
H
G
F
E
D
C
B
A
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DRAWN BY
SIZE
DWG NO
REV
TITLE
SHEET
of
A2
LG Electronics
Date
LGE Internal Use Only
LGM700TV
User Name
1.0
Drawing Date
PDM NUMBER
78
Содержание LG-M700TV
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