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3. TECHNICAL BRIEF
3.6 MEMORY(H8BCS0QG0MMR, U100)
The device is offered in 1.8 V Vcc Power Supply, and with x16 I/O interface. Its NAND cell provides the most
costeffective solution for the solid state mass storage market. The memory is divided into blocks that can be
erased independently so it is possible to preserve valid data while old data is erased.
The device contains 1024 blocks, composed by 64 pages. A program operation allows to write the 1056 words
page in typical 200 us and an erase operation can be performed in typical 2.0 ms on a 128 K byte block.
Data in the page can be read out at 45 ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration
towards different densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, RE ALE and CLE input pin. The
on-chip Program/Erase Controller automates all program and erase functions including pulse repetition,
where required, and internal verification and margining of data. The modify operations can be locked using
the WP input.