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PIN DESCRIPTIONS
Name
Pin NO.
Type
Descri pti on
Power and G roun d
PLL_AVDD 2
Analog
Power
PLL analog power supply. 2.5V supply voltage.
PLL_AVSS 5
Analog
Ground
PLL analog ground.
PLL_DVDD 1
PLL
Power
PLL peripheral digital power supply. 2.5V supply voltage.
PLL_DVSS 6
PLL
Ground
PLL digital ground.
PLL_AGS 4
PLL
Ground
PLL Analog Ground Sensing.
VDD
11,38
Power
2.5V Digital power supply. Core power supply.
VSS
12, 37
Ground
Core digital ground.
IO_VDD
13,27,46
Power
3.3V Digital power supply. I/O power supply.
IO_VSS
12,20,30,45
Ground
I/O digital ground.
System Servi ces
/RESET 10 I
H/W
reset
signal.
Active Low Schmitt-Trigger input.
The Schmitt-Trigger input allows a slowly rising input to reset the
chip reliably. The RESET signal must be asserted ‘Low’ during
power up. De-assert ‘High’ for normal operation.
CLK_IN
48
I
External clock input. 12.288MHz is recommended.
When the PLL_BYPASS is “LOW”, the external clock input from
CLK_IN is used as PLL reference clock source. The external
oscillator generates 12.288MHz clock and the internal PLL
generates 98.304MHz (12.288MHz x 8) system clock.
SA
7
I
Slave Address Set for Host Interface
PLL_EXT_LPF
3
Analog
External PLL low pass filter pin.
PCM Audi o Input/Outp ut I nterface
MLRCK
14
I/O
PCM Word clock (left-right clock) input/output of main 2-channel
audio. User can select the master/slave mode of this signal.
Schmitt-Trigger input.
MBCK
15
I/O
PCM bit clock input/output of main 2-channel audio.
User can select the master/slave mode of this signal.
Schmitt-Trigger input.
MSDIN
16
I
PCM serial data input of main 2-channel audio.
Schmitt-Trigger input.
SLRCK
17
I/O
PCM Word clock (left-right clock) input/output of sub 2-channel
audio. User can select the master/slave mode of this signal.
Schmitt-Trigger input.
SBCK
18
I/O
PCM bit clock input/output of 2-channel audio.
User can select the master/slave mode of this signal.
Schmitt-Trigger input.
SBCK
18
I/O
PCM bit clock input/output of 2-channel audio.
User can select the master/slave mode of this signal.
Schmitt-Trigger input.
SSDIN
19
I/O
PCM serial data input of sub-channel audio.
User can set this sub-channel data input pins to PCM serial data
output pins. See the Control Register Description part.
Содержание LF-U850A
Страница 18: ... BLOCK DIAGRAM 2 12 2 13 ...
Страница 19: ...2 14 2 15 SCHEMATIC DIAGRAMS MAIN SCHEMATIC DIAGRAM ...
Страница 20: ...2 16 2 17 FRONT SCHEMATIC DIAGRAM ...
Страница 21: ...2 18 2 19 SMPS SCHEMATIC DIAGRAM ...
Страница 22: ...2 20 2 21 CD PART WMA MODULE ...
Страница 23: ...2 22 2 23 USB PART ...
Страница 24: ...2 24 2 25 WMA USB BLOCK DIAGRAM ...
Страница 25: ...2 26 2 27 WIRING DIAGRAMS ...
Страница 26: ...2 28 2 29 PRINTED CIRCUIT DIAGRAMS MAIN P C BOARD COMPONENT SIDE ...
Страница 27: ...2 30 2 31 MAIN P C BOARD SOLDER SIDE ...
Страница 28: ...2 32 2 33 SMPS P C BOARD ...
Страница 29: ...2 34 2 35 FRONT P C BOARD ...
Страница 30: ...3 36 3 37 CD P C BOARD COMPONENT SIDE CD P C BOARD SOLDER SIDE ...
Страница 31: ......
Страница 35: ... 4 2 ...