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SiI141B
SiI141B
80-pin TQFP
(Top View)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DE
Q20
Q21
Q22
Q23
OGND
Q24
OVcc
Q25
Vcc
Q26
Q27
Q28
Q29
Q30
Q31
Q32
Q33
Q34
Q35
Q4
Q3
Q2
Q1
Q0
OVcc
VSYNC
OGND
HSYNC
GND
CTL3
CTL2
CTL1
SCDT
DFO
PIXS
OGND
PDO
PD
RESERVED
Q19
Vcc
Q18
GND
ODCK
Q17
Q16
Q15
Q14
Q13
Q12
Q1
1
OVcc
Q10
OGND
Q9
Q8
Q7
Q6
Q5
Vcc
GND
A
Vcc
RX2+
RX2-
AGND
RX1+
RX1-
A
Vcc
RX0+
RX0-
AGND
RXC-
RXC+
HSYNC_DEJTR
EXT_RES
PVcc
PGND
ST
OCK_INV
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
24-bit Input Data for 1-pixel/clock mode
18-bit Odd Data for 2-pixel/clock mode
8-bit Channel 2 Data
1-pixel/clock
6-bit Odd Channel 0
Data 2-pixel/clock
6-bit EVEN Channel 0
Data 2-pixel/clock
6-bit Odd Channel 1
Data 2-pixel/clock
6-bit Odd Channel 2
Data 2-pixel/clock
6-bit Even Channel 2
Data 2-pixel/clock
6-bit Even Channel 1
Data 2-pixel/clock
8-bit Channel 1 Data
1-pixel/clock
8-bit Channel 0 Data
1-pixel/clock
DIFFERENTIAL SIGNAL
CONTROL
GENERAL
PURPOSE
CONTROL
MISC.
Pin Diagram
ST
PIXS
DFO
OCK_INV
PDO
EXT_RES
RX2 +
RX2 -
RX1 +
RX1 -
RX0 +
RX0 -
RXC +
RXC -
HSYNC_DEJTR
Q[35:0/23:0]
ODCK
DE
HSYNC
HSYNC
VSYNC
VSYNC
SCDT
CLT1
CLT1
PLL_SYNC
CLT2
CLT2
DE2
DE1
DE0
CLT3
CLT3
Termination
Control
DATA
RECOVERY
CH2
INTER-
CHANNEL
SYNC.
PANEL
INTER-
FACE
LOGIC
DECODER
DATA
RECOVERY
CH1
DATA
RECOVERY
CH0
VCR
VCR
VCR
VCR
PLL
8
8
8
24/36
Black Diagram
Содержание LB504N-XL
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